How to fix: Error: Mass erase operation failed. / verify flash protection
After evaluating/flashing the SBSFU examples on the NUCLEO-G071RB evalboard it's not possible to erase full flash anymore. I get the error below. How to set factory defaults that erasing is possible again?
STM32_Programmer_CLI.exe -c port=SWD -e all
-------------------------------------------------------------------
STM32CubeProgrammer v2.12.0
-------------------------------------------------------------------
ST-LINK SN : xxxxxxxxxxxxxxxxxxxxxxx
ST-LINK FW : V2J40M27
Board : NUCLEO-G071RB
Voltage : 3.21V
SWD freq : 4000 KHz
Connect mode: Normal
Reset mode : Software reset
Device ID : 0x460
Revision ID : Rev B
Device name : STM32G07x/STM32G08x
Flash size : 128 KBytes
Device type : MCU
Device CPU : Cortex-M0+
BL Version : 0xB2
Debug in Low Power mode enabled
Mass erase ...
Error: Mass erase operation failed.
Please verify flash protection
STM32_Programmer_CLI.exe -c port=SWD -ob displ
-------------------------------------------------------------------
STM32CubeProgrammer v2.12.0
-------------------------------------------------------------------
ST-LINK SN : xxxxxxxxxxxxxxxxxxxxx
ST-LINK FW : V2J40M27
Board : NUCLEO-G071RB
Voltage : 3.21V
SWD freq : 4000 KHz
Connect mode: Normal
Reset mode : Software reset
Device ID : 0x460
Revision ID : Rev B
Device name : STM32G07x/STM32G08x
Flash size : 128 KBytes
Device type : MCU
Device CPU : Cortex-M0+
BL Version : 0xB2
Debug in Low Power mode enabled
UPLOADING OPTION BYTES DATA ...
Bank : 0x00
Address : 0x40022020
Size : 112 Bytes
██████████████████████████████████████████████████ 100%
OPTION BYTES BANK: 0
Read Out Protection:
RDP : 0xAA (Level 0, no protection)
BOR Level:
BOR_EN : 0x0 (Configurable brown out reset disabled, power-on reset defined by POR/PDR levels)
BORR_LEV : 0x3 (BOR rising level 4 with threshold around 2.9 V)
BORF_LEV : 0x3 (BOR falling level 4 with threshold around 2.8 V)
User Configuration:
nRST_STOP : 0x1 (No reset generated when entering Stop mode)
nRST_STDBY : 0x1 (No reset generated when entering Standby mode)
nRST_SHDW : 0x1 (No reset generated when entering the Shutdown mode)
IWDG_SW : 0x1 (Software independant watchdog)
IWDG_STOP : 0x1 (IWDG counter active in stop mode)
IWDG_STDBY : 0x1 (IWDG counter active in standby mode)
WWDG_SW : 0x1 (Software window watchdog)
RAM_PARITY_CHECK: 0x1 (SRAM parity check disable)
nBOOT_SEL : 0x1 (BOOT0 signal is defined by nBOOT0 option bit)
nBOOT1 : 0x1 (Boot from Flash if BOOT0 = 0, otherwise system memory)
nBOOT0 : 0x1 (nBOOT0=1)
NRST_MODE : 0x3 (Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode))
IRHEN : 0x1 (Internal resets drives NRST pin low until it is seen as low level)
PCROP Protection:
PCROP1A_STRT : 0x0 (0x8000000)
PCROP1A_END : 0x0 (0x8000200)
PCROP_RDP : 0x1 (PCROP zone is erased when RDP is decreased)
PCROP1B_STRT : 0xFF (0x801FE00)
PCROP1B_END : 0x0 (0x8000200)
Write Protection:
WRP1A_STRT : 0x0 (0x8000000)
WRP1A_END : 0x0 (0x8000000)
WRP1B_STRT : 0x3F (0x801F800)
WRP1B_END : 0x0 (0x8000000)
FLASH security:
BOOT_LOCK : 0x0 (Boot based on the pad/option bit configuration)
SEC_SIZE : 0x0 (0x8000000)
