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Hi, I am using the STM32N6570-DK development kit and I want to flash my FSBL and Application firmware into external flash using USB. Currently, I am able to flash the firmware using ST-LINK, but I want to perform flashing through USB as well. I configured the boot pins as mentioned in the datasheet: BOOT0 = High BOOT1 = Low Current behavior The device is detected in STM32CubeProgrammer when connected via USB. USB connection is successful. Partitions such as FSBL, RSSE_FW, RSSE_BLOB, RSSE_PLUGIN, etc., are visible. However, the Download / Erasing & Programming option is disabled. Questions Is flashing external flash through USB supported on STM32N6570-DK? Do I need to configure any OTP boot source or BOOTROM settings to enable USB flashing? Any guidance or examples on how to enable external flash programming via USB would be very helpful.Thank you.

 Hey ST-Community,I’m working with an STM32H7S78-DK board and trying to get Ethernet running. TouchGFX and FreeRTOS are working fine, but I’m stuck with lwIP. The task starts, but DHCP never succeeds (the printed IP is always 0.0.0.0). I also tried with a static IP, but I still can’t ping the board. Deactivating TouchGFX didn't help.I've followed this video: STM32 : How to Get an IP Address via DHCP on STM32H7S78-DK with LwIP using IAR EWARMLwIP has the following memory settings:MEM_SIZE = 14*1024BytesTCPIP_THREAD_SIZE = 4 * 1024BytesI've configured the MPU as well following the given Video.I’m not sure where to look next – maybe I’m missing some configuration step? Has anyone successfully used lwIP with this board and could give me a hint?Thanks a lot in advance!

I am trying to understand SMiRoT and SMuRoT for product development based on the STM32H573 and Secure Manager, but from the public documentation they both look mostly like black boxes.Since they seem to be built on top of STiRoT / STuRoT, I am currently trying to understand STuRoT first.For STiRoT, AN6007 Appendix A / Figure 11 is very useful because it provides a clear high-level startup sequence.It helps explain the logic of reset, runtime protection activation, secure firmware update handling, uRoT image verification, bootloader fallback, and jump to uRoT.But for STuRoT, I cannot find any equivalent public document that shows its internal startup sequence or high-level state flow.At the moment I can only infer that after STiRoT verification, STuRoT runs in HDPL2 secure mode, reconfigures its secure context/MPU, verifies the user application, and then executes it. But I have not found an official flowchart or sequence description.So I would lik

I am currently working on an STM32-based project using UART for continuous data transmission between the microcontroller and a PC application. The system works fine initially, but I am facing intermittent data loss and incomplete packets during long-running communication. The issue becomes more noticeable when the baud rate is increased or when multiple interrupts are active in the system. What I have already tried: Verified baud rate and clock configuration in STM32CubeMX Enabled UART interrupt-based receiving Increased buffer size for RX handling Checked wiring and physical connection stability Despite this, the problem still occurs randomly after some time of operation. I would like to ask the community: What are the best practices for stable UART communication in STM32 under continuous data flow? Should I switch to DMA-based UART instead of interrupt mode for better reliability? Are there any known issues with buffer overflow or interrupt priority that could cause this behavior?

Hi,    I bought VIPER06LN from mouser. Please help me check the COD. The Chinese custom need this information.   Thank you

I am using STM32C071FBP6N MCU TSSOP 20 pin package for one of our project.I am observing Pin_20 is muxed with lot of other pins like PB3/PB4/PB5/PB6. if i select PB3 as GPIO_Output using STM32CubeMx and generated a code. If i try to toggle the pin but its not working at all, none of the peripheral on that pin for PB3 is working. But if i select PB6 as GPIO_Output i can able to toggle or modify.This issue is not only with Pin_20, same with Pin_1 also which shares with PB7/PB8, only PB7 is working.I have tried with multiple chips what could be wrong in this scenario??

I am generating a PWM signal using timer1 register and use it in Center aligned mode. I want to to know if i can modify the timer counter register TIMx_CNT register with some "x" value in the timer interrupt instead of resetting it to 0. 

Hello I am trying to implement I²C slave on a STM32U385RGTxQ in non-blocking mode, on I2C2.To match I²C standard I tried to use the Address macthed interruption but the interruption is never trigged. I used the function HAL_I2C_EnableListen_IT(&hi2c2) to enabled it; My issue is, I don't reach neither the I2C2_EV_IRQHandler(void), the I2C2_ER_IRQHandler(void) or the HAL_I2C_AddrCallback() when sending the slave address.  Please found attached my project. And bellow some pictures of my I2C2 init, an oscilloscope capture and my I2C2 register when I am in debugger :         Best Regards Thibaud HABRAND      

Hi,I'm designing a board with STM32MP153FAD and have a question about DDR layout reference.Which reference should I follow for the DRAM section?Eval kit MB1272C_03 layoutST's published reference DDR layout.Questions:Which is the recommended reference for custom board design?Is there a design guide specifically for STM32MP153 DDR layout and routing guidelines?Is there a document listing pin delays for the FAD series SoCs? This would be helpful for length matching calculations.Best regards,Batuhan

Hello,I've just received my fresh new SMT32H747I-DISCO dev board and I wanted to try some samples.I have some experience deveolping on embedded Liuxes, but this is my second MCU (the first one was a Raspberry PICO, don't know if this counts). I am using a MacBookPro with Apple silicon (M3) and MacOS 14.4What I have done:read the specs, configured the board to get power and STLink from CN2 (as is by factory)installed every tool available:STM32CubeProgrammerSTM32CubeIDE (which also installed a SMTLink server nstall ,st-stlink-server.2.1.1-2, installed successfully ) even STM32CubeMXconnected the board to a USB-C port on my Mac via a USB-C to USB-B mini cable2 times out of three the main led (LD10?) starts red, then flashes red/green then stays green. The other times the board LED stays red. In either case, nothing on the LCD display. to me the board seems waiting.On the former occurrences, MacOS then asks me for permission to connectbut that's it. I wanted to install the Tutti Fruit

I am not able to erase a section of internal flash of the NUCLEO-H633RE.Using the debugger I see the Flash is all 0x00 before I try to erase.  I verify that Flash is not locked i.e.if (*FLASH_NSCR && LOCK) { *FLASH_NSKEYR = 0x45670123; *FLASH_NSKEYR = 0xcdef89ab; }then I try to erase a section of Flash i.e./* ************************************************************************* */ /* */ /* EraseFla - Erases 8K page of Flash, Waits for Flash not busy. */ /* Inputs: uint32_t page holds the page to erase. */ /* Outputs: None */ /* */ /* ************************************************************************* */ void EraseFla(int EraPage) { while (*FLASH_NSCR && BSY){}; n = *FLASH_PRIVCFGR; // just testing n = EraPage >> 7; if (n && 0x0800) { n &= 0x07C0; n |= 0x80000004;} // BKSEL and SER else { n &= 0x07C0; n |= 0x00000004;} *FLASH_NSCR |= n; *FLASH_NSCR |= STRT; while (*FLASH_NSCR && BSY){}; }  With the debugg

English language:STM32H7 Ethernet + DMA + Cache Explained + LwIP (EN) One of the most common sources of confusion when working with STM32H7 microcontrollers and Ethernet (via LwIP + HAL ETH) is data cache (D-Cache) behavior.When using DMA (like Ethernet MAC DMA), if D-Cache is enabled (which it is by default in STM32H7 projects), you must manage cache coherency manually. Otherwise, the DMA peripheral and the CPU will not agree on what data is in RAM.I encountered this exact issue myself and spent significant time identifying the root cause. Since many others using STM32H7 are likely to face this same problem, I'm sharing this explanation to help save your time and effort.Problem:If you fill a pbuf->payload buffer with data and send it using HAL_ETH_Transmit() without cleaning the D-Cache, the CPU will still be holding the most recent data in its cache, but the DMA will read stale or uninitialized data from RAM.Result: corrupted Ethernet frames, broken ping replies, UDP iss

Hey!Does anyone recognice this part?It`s marked with C306 (ST- Sign) FRO169.It looks like a transistor or diode in SOT-229 package.Thanks!Frank

Hello, I am trying to setup TIM5 channel 1 to output a signal on its output pin. I generated the code using STM32CubeMX2. I am getting an assert failed during initialization.mx_system_init() calls mx_tim5_init() which calls HAL_TIM_OC_SetConfigChannel(): oc_config.polarity = HAL_TIM_OC_HIGH; oc_config.idle_state = HAL_TIM_OC_IDLE_STATE_RESET; if (HAL_TIM_OC_SetConfigChannel(&hTIM5, HAL_TIM_CHANNEL_1, &oc_config) != HAL_OK) { return NULL; } In HAL_TIM_OC_SetConfigChannel function assert fails at the following line: ASSERT_DBG_PARAM(IS_TIM_OC_OVERRIDE_STATE(p_config->override_state)); ASSERT_DBG_PARAM(IS_TIM_OC_BREAK_MODE(p_config->break_mode));The value of the override_state shown by the debugger  is: (HAL_TIM_OC_OVERRIDE_SET | unknown: 0xfa). If I comment out the assert it will assert on the next line (break_mode). If I comment that line out as well the code outputs a signal on the pin. I attached my MX2 file. What am I missing?-Gil 

Hi all, Thank you for looking at my thread.I have started a proof of concept project that runs ThreadX and TouchGFX on a custom QSPI display on STM32F7. I noticed from the documentation at https://support.touchgfx.com/docs/development/touchgfx-hal-development/scenarios/scenarios-configure-rtos that the following warning is highlighted.Now indeed when I generate the code from CubeMX the MX_TouchGFX_Init is not getting called from anywhere, and in the documentation it suggests to call it from app_azure_rtos.c in the tx_application_define method.However in such method the main thread is already been initialized.If i replace App_ThreadX_Init with MX_TouchGFX_Ini, I am getting a TX_POOL_ERROR.What am I supposed to do to initialize TouchGFX?Thank you 

Hello,The latest version of STM32CubeMX no longer lists x-cube-spn5 as an available package.Could someone help me how to use a X-Nucleo-IHM05A1 expansion board with the latest tools please? 

Good morning everyone, I have this Mini STM32F103C8T6 CH340 board which supposedly has the original chip (photo), I configure it as suggested in a post I saw here but it gives an error (attachment).Does anyone have a solution?Edited to place Images in-line for easier viewing:  

Hello everyone,I am developing a UI using TouchGFX on a custom board based on the STM32F767. I am encountering visual artifacts during screen updates.As seen in the attached video:In the date selection wheel, the text overlaps, tears, and leaves ghosting artifacts during scrolling.The first menu ("Date & Time", "Language" etc.) is inside a ScrollableContainer with a ListLayout. Initially, the text is corrupted. However, as soon as I scroll this container, the artifacts disappear completely and the screen draws correctly.System Info:MCU: STM32F767GUI: TouchGFX (Version: [Sürüm] )Memory: Framebuffer is located in [SDRAM vb.]Configuration: MPU is ENABLED, D-Cache is ENABLED.What could be causing this issue? Any suggestions on which configurations or settings I should check?Thank you!

Hi everyone,I'm experiencing a very specific bus/clock issue on a custom board using the STM32U5G9ZJ (and also tested on STM32U5F9ZJ).The Problem: My display (320x240, RGB565 via LTDC) only works if the HSPI1 peripheral is enabled in CubeMX. As soon as I disable HSPI1 (which I need to do to free the PH9 pin for power management reasons), the screen turns grey, even though the LTDC settings remain unchanged.Key Technical Details:Data Location: All assets (images/fonts) are stored in Internal Flash memory. The HSPI/OctoSPI bus is NOT used during the display process.Memory Status: In Debug mode, I can confirm via the Memory Browser that the Frame Buffer (located at 0x20025800) is correctly populated with pixel data.LTDC Behavior: Despite the RAM being correct, the LTDC fails to output data to the panel when HSPI1 is OFF.Configuration: Pixel Clock (PLL3R) is at 200MHz, GPIOs are "Very High Speed", and the Frame Buffer is placed to avoid conflicts with the RTOS (ThreadX) heap.The Mystery: W

We have some devices based on STM32MP257 SoCs that connect to a 100 Mbit Ethernet network via ETH1, where ETH1 is going straight to an RMII PHY. Pins for ETH2 are reserved, but are not used/not connected. Some of our devices work rock-solid as excepted, but others exhibit massive performance problems on the Ethernet connection.After lots of research, we think that our devices are affected by a silicon bug described in errata sheet ES ES0598 as "ETH1 RMII mode could have CRC errors". Our chip revisions are all rev Y, which are affected by the issue. The errata says that ETH1 should be routed through ETHSW to work around the silicon bug. To test if the workaround works for our case, I've tried to enable ETHSW, but failed so far because STM32CubeMX forces me to free some pins before it allows me to enable ETHSW in RMII mode. It seems like ETH1 and ETH3 must be used together if ETHSW is enabled, the pins for ETH3, however, are already used for other hardware functions.So, my goal is to- en

Hello!I have implemented one of the key parts of a speech recognition system on the STM32N6 without using the cloud. I would like to describe my results in more detail, but it seems to me that the “New Message” section is not the right place for that. Could you please advise me where it would be better to share this? 

Hello,I want to know the DAC output buffer maximum safe output current before damaging the output buffer. I know that it's not possible to get the output swing mentioned in the datasheet under this condition.The datasheet maximum ratings doesn't state it for the DACs, and from the normal ratings only the current to keep the maximum output voltage around VREF+ can be calculated. So, either I wasn't able to locate the information in the datasheet (which is hopefully the case) or it isn't mentioned there at all.I'm using a STM32U083 device, datasheet https://www.st.com/resource/en/datasheet/stm32u083kc.pdfRegards

I created the project in TouchGFX 4.26.0 Designer, modified pins with CubeMX_17, and attempted to debug the project in STM32CubeIDE 2.1.1. The example I used was Flex Button Example.Kit is STM32U5G9J-DK2.When I attempt to set up a debug configuration in CubeIDE, I am unable to select a project. This project compiles and works when I flash it to my kit through TouchGFX. Could there something wrong with my project structure? Thank you. 

Hello, Using STM32F4 USB USB_OTG_HS, PCD_SPEED_FULL for USB Device CDC we are transmitting data to Host.After some minutes the transmission gets stuck. Although the TXFE IRQ is received, no XFRC IRQ happens and consequently TX state is not set back to 0. The DTXFSTS counter stays on 0x40 (empty is 0x80).The USB trace looks normal. When the problem occurs the peripheral answers all IN Transactions with a NAK.Why does the peripheral not transmit the data but does NAK instead?The problem is seen with different types of Hosts (PC or other embedded devices).Attached Log Output and Screenshot of the Trace.HAL 2.4.2 us used. The TxState fix was applied (Enable/Disable IRQ moved to USBD_CDC_TransmitPacket)Many thanks for any help.

For our product we use sliders to set parameters in our software. Some parameters effect the range of others at runtime. Sometimes the allowable range of the values is limited to a single value. In such a case min equals max. This leads to an assert error in the simulator and undocumented behavior on the target.We would like to see support for min=max. One way to implement it is to show the Indicator Image in the center (or left),  disable sliding, and set the value=min=max. This would simplify our firmware since we wouldn't need to handle it as a special case.I also added the tag bug-report since undefined behavior on the target is unacceptable.