STM32 MCUs Products

STM32C071GBU6 PA2 (pin 8 on the UFQFPN28 device) is configured as ADC_IN2.  What voltage can be expected when the pin is unloaded?

Hello,I have strange behavior with reset, with reset pin, NVIC_SystemReset() or then IDWG fires the MCU just stops and do not restarts with debugger connected or without, when debugger is connected and toggle reset there text is displayed what address is out of scope, where to search for problems ?Reset pin is connected to 100nF capacitor, oscilloscope do not detect any activity on RST pin then NVIC_SystemReset() or IDWG firing, to connect with cubeProgrammer or upload code from cubeIDE I have to keep reset low and then turn on power, later until power is not disconnected there is no problems to connect and upload code many times.If before power applied reset is keept low and then released the code do not loads, but I can connect with debugger and upload code.If at power up reset is not low then code starts normally, the FSBL and then APPLI starts like expected.The main problem about reset problems what IDWG do not restarts MCU, MCU

HIUsing stm32f303veh6.Changed the option bytes with the CubeProgrammer. 2.20.0 to override the BOOT0 signal. ( its floating )nBOOT1 - > uncheckedBOOT_SEL -> unchecked I see that the address on start is 0x1FFFF.. and my FW on flash does not run. For debug, I I did some external wiring of the BOOT0 signal to GND, and now my FW boots fine.Looked in Errata for know issues, but could not find any related. Any reason for Option Bytes not to work?   

Hello,Regarding the STM32N657, I'm not using the internal SMPS.  My question is:  Do we need to put capacitors on the 6 VDDSMPS pins or can they be left as no connect?   Same question on the VLXSMPS pins... do we need the capacitors on these pins, or can they be left as no connect?Also, on the STM32N657-DK board, there is a snubber circuit on the VLXSMPS pins, why?Finally, when I say "No connect", I assume these pins are connected internally, so it does not require an external link on the PCB when not used.  Is this correct?  (this will probably make the routing of the PCB easier)We are dealing with a

Hello Everyone,I am facing an issue with my MCU entering low-power mode.My idea is to freeze the Independent Watchdog (IWDG) counter in STOP mode so that the MCU will not reset due to the IWDG counter elapsing.From my understanding, this can be achieved by clearing bit 17 (IWDG_STOP) of the FLASH_OPTR register, if I am right. As per the reference manual, in STOP mode, the IWDG can be automatically frozen depending on the configuration of the IWDG_STOP bit in the

I'm using SPI3 and TIM3's PWM CHANNEL 1 on PB4.after HAL called __HAL_RCC_SPI3_CLK_ENABLE(), the PWM output disappeared...I want to know how to fix this.

Hello,I'm using the STM32N657 processor and have the HEXASPI device running at 1.8V.  VDDIO2 is connected to 1V8 supply (which affects: PO[5..0] and PP[15..0]The FMC is placing the A23 line on pin PO1 (this is the only option for the FMC-A23) and the FMC device is running at 3.3V.   Can I place a pullup to 3.3V on PO1, or will this affect/blow  the GPIO connected to 1.8V -OR- do I need to place a voltage translator on that pin?  

I drew a board of stm32h503rbt6, including a screen and a NOR flash. The flash model is mxl6433f. Currently, the problem I'm facing is that when I try to program the board using stprogram, I encounter an error that the programming cannot be completed. The error message shows that the memory deletion failed. I have been looking into it for a week, but still haven't been able to solve it. I hope a senior can help me with it.I'm really in a bad mood right now. 

Heyho,strange things happening that I'd like to understand for a STM32L073 (Nucleo for now).Setup on a L073 @ 32MHz:- ADC is clocked by PCLK/4- ADC prescaler = 2 -> divide by 4 -> 2 MHz- 12 bit right aligned- ref V = VDDA = 3.3V- hardware oversampling + shift is used (great feature!)- 7 ADC channels sequenced- DMA, with buffer for 8 samples per channel -> u16AdcDmaBuf[56] In non-circular mode (CIRC neither set in DMA- nor in AD-registers), after each DMA's transfer complete interrupt, DMA and ADC are restarted, everything is as it should be, and as it is set in the sequencing registers.Here's what the DMA buffer looks like, and all this makes sense:buffer[0] = 2031 is the DAC output set to 2047,buffer[1] & buffer[2] = 4095 are connected to VDDA -> 4095 ok,buffer[5] is internal VREF = 1.2V -> perfect,buffer[6] is internal temperature sensor -&

Hello! I am working on a custom OTA bootloader system on a STM32G473RBT6 MCU in a custom board I have been using maybe for 3 years with no problem. My board is connected to a Raspberry Pi over RS485 network. My idea is this:There are 3 virtual sections: 24 KB OTA Bootloader starting from 0x0800 0000. 52 KB Storage space starting from 0x0800 6000 and 52 KB Application space starting from 0x0801 3000. In total 128 KB as the STM32G473RB MCU has.The custom bootloader reads incoming data, erases storage space and stores this new data in storage space, check CRC32, etc. Then the bootloader erases previous application in application space, and copies storage space to application space and starts from new application address.The problem is that the bootloader only succeeds if the following condition met (basically full flash erase):I have a fully erased chip and only bootloader loaded. If I want to load a simple LED blink application which FLASH

Hey everyone,I’ve been using the STM32F429IGT6 for an audio project, and I'm running into an issue with the ADC readings. When the system is idle, everything seems fine, but once the load increases, the readings start to fluctuate unexpectedly—particularly when using I2C.I’ve already tried adding decoupling capacitors and adjusting the wiring, but the issue still persists. Wondering if anyone has dealt with similar issues, especially related to power noise or grounding, and how they managed to stabilize the ADC?Any advice would be great!Thanks!

Hi,I would like to recreate the DCMIPP_ContinuousMode example but using the cubeMX to configure the MCU, I haven't found anything online to follow as example.Thanks.

Hey together, I have a question regarding changing the clock while running in XiP mode. Upfront everything works so far very well. On our STM32H750 we have a very simple bootloader. This bootloader configures the QSPI and the STM32H7 to run the appliction code in XIP. Therefore we configure the QSPI clock to use the HCLK3 in the bootloader. We use an external crystal 8MHz and the PLL as SYSCLK to generate the 240MHz for the HCLK3. Then we jump to the application code. The applicaiton code resets the System Clock Mux in the startup code calling "SystemInit ()" inside the system_stm32h7xx.c to use the HSI (64MHz) for SYSCLK. This results at first in a drop of external crystal signal as well as a clock drop of the QSPI Clock from 240MHz to 64MHz. Then we reconfigure in the application code, while running in XiP, the System Clock Mux to use the external crystal and the PLL. Going back to the 240MHz for the QSPI. So

Hi everyone, I’m working with a custom made STM32F446ZET6 board that otherwise functions perfectly (all peripherals, flash programming, etc. work fine). The only thing that doesn’t is the ROM bootloader. I can’t get USB DFU or UART boot to respond no matter what I do. What I’ve verified BOOT0 = 1 (3.3 V) at reset NRST pulled high, no reset loops VDDUSB = 3.3 V, decoupled with 100 nF HSE = Abracon ABLS-8 MHz-12 pF, started with 18 pF load caps and lowered to 10 pF as I saw in a post here this might be the cause PA9 connected directly to VBUS (5 V)  PA11/PA12 wired to USB-FS D−/D+ (verified routing and continuity) Board runs normal firmware from Flash with n

Hi,I'm exploring using UART idle interrupt on RX to signal to my application that data has arrived.I currently push data into a tx queue then start transmission. I rely on uart tx ISRs to check if there is any more data to send, then load up a DMA transfer.UART TE is enabled once when the UART is enabled. I then rely on DMA to do everything. This currently works very well.Can anyone suggest how I could squeeze and idle frame in? Ideally an idle frame will be inserted after each call to uart_dma_send, eg once per item in the transmit queue. My aim would be to keep my current transmit setup, where I can keep shoveling data into the transmit queue. Im using STM32F745. Probably I've missed something in the datasheet..TX currently looks like:void interface_uart_send_stuff(if_uart_t* p, uint8_t* stuff, uint16_t length) { tx_q_push(p, length, stuff); if (tx_state_is_busy()) { // TX already happening, ju

I am trying to use one STM32M4 as TX, and another STM32M4 as RX,but RX can't receive the correct i2s data that TX transmits.TX transmits 16bits data by HAL_I2S_Transmit_IT(&hi2s2, i2s_dummy_buffer, 16);RX receives 16bits data by HAL_I2S_Receive_DMA(&hi2s2, i2s_received_buffer, 16); The results:1) If TX transmit 0,1,2,...,15:RX receives:[0] = 0xC000 [1] = 0x0000 [2] = 0x4000 [3] = 0x8000[4] = 0xC001 [5] = 0x0001 [6] = 0x4001 [7] = 0x8001[8] = 0xC002 [9] = 0x0002 [10]= 0x4002 [11]= 0x8002[12]= 0x

Hello,In AN5967, it says:When VBAT is connected (VBAT = 3.0V)?  will the oscillator (RTC) stop running if VDDA18AON is not present?There are several conflicts between the various documents... Can someone at STM update the docs?AN5967,  RM6486, UM3300, and the STM32N657x0-dk development board schematics seem to contradict each other.... which one is correct regarding the SMPS configuration?

I am unable to control GPIO output pins with the H5 GPDMA.  I am able to control GPIO with the F103 using this project...https://github.com/mnemocron/STM32_PatternDriver...where the DMA is much simpler.  Section 3.7 of AN5593 (How to use the GPDMA for STM32 MCUs) doesn't provide much information on GPIO control, but does mention using memory-to-memory transfers.  I have tried both memory-to-memory and memory-to-peripheral circular DMA transfers without success.  Like the F103 example, I am using the TIM2 output compare CH1 as the request event for a DMA transfer.  My scope indicates that TIM2 CH1 is toggling properly every millisecond, but no signal comes from the GPIO pins.  I've tried myriad permutations of modes and requests/triggers with no success.Can someone please provide help or a link to a GPDMA project that

So new problem while trying to bypass non functioning SWD...Using a working NUCLEO_H723 I can use the STM32CubeProgrammer to access it via STLINK (internal and external) as well as via USB DFU after reset with BOOT0 high.From my reading of AN2606, once the bootloader has initialized, it cycles through the various options in sequence till it gets a connection (CAN first, then USARTx, I2Cx, SPIx, USB). The diagram indicates USB cable detection so I'm assuming as long as it isn't connected that the other peripherals will be checked.I'm unclear on it checks all the possibilities for each USARTx (and I2C, SPI) or just one of them ? The only readily accessible USART is UART3 on CN10 of the Nucleo so I've started with that. Tried using RTS/DTR for BOOT0 and reset control but can't get the timing/polarity correct so just holding BOOT0 high and tried both manual reset and a pulse from DTR. I can see a single 0x7F being sent but no reply, then one more 0x7F after 2 second

Here is the code:  void DMA_Init_SPI2(void *rxBuffer, void *txBuffer, uint16_t rxSIZE, uint16_t txSIZE) { RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN | RCC_AHB1ENR_DMAMUX1EN; // DMA1 Channel 1 для SPI2_RX (Peripheral-to-Memory) DMA1_Channel1->CCR = DMA_CCR_MINC | // RAM++ DMA_CCR_TCIE | // IRQ_EN DMA_CCR_PSIZE_0 | // 16-bit DMA_CCR_MSIZE_0 | // 16-bit DMA_CCR_CIRC ; DMA1_Channel1->CNDTR = rxSIZE; DMA1_Channel1->CPAR = (uint32_t)&(SPI2->DR); DMA1_Channel1->CMAR = (uint32_t)rxBuffer; DMAMUX1_Channel0->CCR = 12 ; // SPI2_RX (Table 91 rm440) // DMA1 Channel 2 для SPI2_RX (Memory to Peripheral) DMA1_Channel2->CCR = DMA_CCR_MINC | // RAM++ DMA_CCR_DIR | // RAM -> SPI DMA_CCR_PSIZE_0 | // 16-bit DMA_CCR_MSIZE_0 // 16-bit ; DMA1_Channel2->CNDTR = txSIZE; DMA1_Channel2->CPAR = (uint32_t)&(SPI2->DR); DMA1_Channel2->CMAR = (uint32_t)txBuffer; DMA

I have an STM32G431 doing FOC on a little gimbal motor, but am getting strange noise on the current sense ADC when it's being triggered by TIM3. It shows up as random spikes, which values always end up being dividable by 8. Weird thing is, if I have the ADC set to oversample, it will average out these spikes. While I'm 100% sure it's a digital artifact, not measured noise. That would never ever all end up with the last 3 bits being "000". Here's a direct comparison by the ADC being triggered by TIM3's TRGO directly:

Hi all, I have an STM32L071VBT6 and want to test the UART functionality. I configured UART4 RX and TX and physically connected them to do a loopback test.  I define 2 arrays to start with /* USER CODE BEGIN PV */ uint8_t Send_buffer[] = "Gateway test"; uint8_t Rec_buffer[13]; /* USER CODE END PV */   I start by clearing the Rec_buffer array. /* USER CODE BEGIN 2 */   memset(Rec_buffer, 0, sizeof(Rec_buffer));   /* USER CODE END 2 */   Then in my while loop I try to send and receive, but I always just receive the first character (

Hi everyone, I’m working on CAN communication using STM32F746 in STM32CubeIDE.My goal is to transmit CAN frames continuously and verify them using BusMaster or PEAK CAN analyzer,but I’m not seeing any CAN frames on the bus. To help review my setup, I have attached my project ZIP file below.Could someone please check and confirm: If my CAN clock configuration is correct Whether the CAN2 TX/RX pins are configured with the right alternate functions If my main.c code for CAN initialization and transmission looks correct Whether I need any filter configuration even if I only want to transmit Setup details: Controller: STM32H746 Interface: CAN1 Mode:

 I remember some other RM suffering from this in the past.JW

As reported here, this is obviously incorrect.Also, this has been already reported by Uwe Bonnes for 'F411/RM0383, which has indeed been corrected in the registers description, but the GPIO register map still contains the incorrect value. So, could ST please go through all low-end 'F4 RM and check/correct at both places where applicable?Thanks,JW@Amel NAS