STM32 MCUs Security

Posted on December 06, 2017 at 21:27Hi there,i have a STM32L063 and i wanna encrypt a 32-byte packet by AES-CBC.I have tested it with using the 'HAL_CRYP_AESCBC_Encrypt' and 'HAL_CRYP_AESCBC_Decrypt' and it worked everytime the same encrypted packet and decrypted packet matches the original packet.Now i have changed to DMA and it worked the first cycle. The Second cycle there is not the expected behaviour.Does anybody have an idea what could be the problem?ThanksHere the code:if (HAL_CRYP_DeInit(&hcryp) != HAL_OK)            {                Error_Handler();            }            MX_AES_Init();//            if (HAL_CRYP_AESCBC_Encrypt_DMA(&hcryp, packet_b_aes,//            AES_PACKETSIZE, packet

Posted on May 11, 2017 at 17:47Recently PolarSSL library has been replaced by mbedtls in STCube Third Party libraries.PolarSSL used to have STM32 specific code for some of the Polar SSL APIs. Now, in the latest STCubembedtls library does not have STM32 specific code which enables usage of hardware HASH and CRYPTO engine.What is the reason for this ?Best regards,Bogdan#stm32 #crypto #mbedtls #hash

Posted on November 24, 2017 at 15:08I have a simple project that toogle a LED. I try to add software protection to it.Basically, it does  :main(){  Init_GPIO_for_LED();  LED_ON();  while(i++ < 10000000) {}; // yes, ugly  LED_OFF();    while(1) {} // wait forever}If I flash it, I see the LED light for some time.Then, I want to protect the program, so I use the ST-Link Utility to switch the RDP to Level 1.$ ST-LINK_CLI.exe -OB RDP=1STM32 ST-LINK CLI v3.0.0.0STM32 ST-LINK Command Line InterfaceST-LINK SN : [edited]ST-LINK Firmware version : V2J24M11Connected via SWD.SWD Frequency = 4000K.Target voltage = 0.0 V.Connection mode : Normal.Device ID:0x429Device flash Size : 64 KbytesDevice family :STM32L100x6xxA/L15xx6xxAUpdating option bytes...Option bytes updated successfully.I perform a hard reset after, and I can see the RDP level is set :$ ST-LINK_CLI.exe -rOBSTM32 ST-LINK CLI v3.0.0.0STM32 ST-LINK Command Line InterfaceST-LINK SN : [edited]ST-LINK F

Posted on November 22, 2017 at 14:23Hello all,Our product is being programmed on test bench and after that it is locked setting the readout protection to level 2 (RDP level 2).My question is - is it normal for this process to take about 3 minutes?Are there any options to speed up this process?The programming unit used is ST-Link v2.Best regards,Martin#long-time #stm32f429 #readout-protection #rdp #rdp-level-2

Posted on October 23, 2017 at 10:41Hi,I'm using X-CUBE-CRYPTOLIB 3.1.0.All RSA_PKCS1v15_* functions uses a 'membuf_stt *P_pMemBuf)' parameter.The documentation says : 'The structure pointed by P_pMemBuf must be properly initialized.'In the examples the buffer use 4096 Bytes.I could not find in the documentation the RAM size needed.I try serval values, but RSA_PKCS1v15_Verify seems to need at least 4096 Bytes.4KB is a lot of memory, for a STM32F103 with 20KB of RAM.Where can I get more information ?Regards,Fred.#x-cube-cryptolib

Posted on October 19, 2017 at 11:21Hello,I am using the STM crypto library X-CUBE-CRYPTOLIB (there are several libraries and I could not find out which one was recommended so I picked the most recent one) with an STM32F417.I can't find any information about the internal implementation. More specifically, I need to know if the AccHw_ AES routines use DMA. The CRYP_IN DMA stream is (2, 6), but my application requires SDIO on the same stream (I can't use stream (2,3) because it is needed by SPI1_TX).My initial testing shows that the encryption seems to work despite the fact that the SDIO is on and active, but I need to understand *why* does it work and if I can rely on this behaviour.Therefore, I have the following questions:- Does X-CUBE-CRYPTOLIB uses DMA for the AES encryption?    - If it does, how can it work in parallel with the SDIO?    - If it does not, why? Does it uses interrupts? Polling? How can this be optimal?- Can it be configured and how?

Posted on October 02, 2017 at 17:36My current project involves some pretty complicated logic, required for firmware update over the air. So I ended up with solution, which contains bootloader and application code, compiled separately. My current memory layout looks like that:And now I should protect bootloader sectors 0 to 3 in such way, that their content cant be modified from application, running in main memory sectors 4 to 7. That situation is unlikely to happen, only in case if some malicious software will be loaded, so the goal is to ensure that even in that case device will restore after power-on-reset. My current idea is to set RDP for entire chip and enable write protection for sectors 0 to 3. But I still have some scenario in mind when malicious firmware can break the device:1) What if the firmware will access some option bytes, somehow turn off the sectors 0 to 3 write protection and then perform mass erase?2) What if the firmware will modify somehow

Posted on September 23, 2017 at 14:10Hello,rm0433 rev 3 and stm32h742xx.h header are not consistant about CRCDATARx.From the description in rm0433 3.3.6, is seem that there are CRDATAR1 and CRCDATAR2.rm0433 3.5 only lists CRCDATAR at offset 0x5c and 0x15c, impying both registers are aliased.FLASH_TypeDef in stm32h743xx.h lists CRCDATA and CRCDATA2.Please clarify.#crc #stm32h7 #flash

Posted on September 21, 2017 at 13:03Hello All,I am using STM32F767ZI Nucleo Board. I am getting DCRCFAIL in data transfer using CMD53 in SDIO.Any possible reason for CRC failure? Could there be any relation to clock out from SDMMC adapter?I am able to see the 1st word in FIFO which seems to be correct. But not able read further bytes.Are there any reference code for SDIO related commands like CMD52, CMD53?regards,Hemanth#crc #stm32f7 #sdio

Posted on March 24, 2016 at 14:16Hi, I cannot manage to enable the RNG that is on my STM32F407VG. Using https://github.com/libopencm3/libopencm3-examples/blob/master/examples/stm32/f4/stm32f4-discovery/random/random.c, setting the RNGEN bit in RNG_CR does not seem to do anything, neither does setting the IE bit. No matter what I try, RNG_CR, RNG_SR and RNG_DR always all read 0. It's hard to debug something like this. Any ideas what it could be?Edit: nevermind, it turned out that having the PLL clock enabled is not sufficient, but that you explicitly have to enable the clock for the RNG peripheral. Thread can be locked/removed. #rng-stm32f4-stm32f407

Posted on July 21, 2017 at 15:49 Hi all : I am using the STM32L4xx Stm Cube drivers for AES-256 ECB encryption on the STM32L4 Although the encrypted data comes out perfectly, the decrypted encrypted data is not the original plaintext. To be clear: I am not using the X crypto library, but instead the https://github.com/labapart/polymcu/blob/master/Device/ST/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp.h and https://github.com/labapart/polymcu/blob/master/Device/ST/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cryp_ex.h modules that are included in the from the STM Cube STM32L4xx HAL Drivers. Some info about the code: -The MX_AES_Init function uses HAL_CRYP_Init to initialize the AESmodule - I am using this API to encrypt and decrypt data: HAL_CRYP_AESECB_Encrypt_IT -After the encryption, I deinit the AES module change the operating mode to decrypt and re init using the HAL init function - I tried setting the original operating mode to decrypt and feeding in the encrypted output, but I

Posted on August 07, 2017 at 13:57Hi forum,For my project, I use the STM32L0G6 MCU. My goal is to program the device, and then protect it against read-out, such that no copy of the firmware can be done.I also use the embedded bootloader ( see http://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf & http://www.st.com/content/ccc/resource/technical/document/application_note/51/5f/03/1e/bd/9b/45/be/CD00264342.pdf/files/CD00264342.pdf/jcr:content/translations/en.CD00264342.pdf) to program the devices. Unfortunately, using read-out protection disables the GO command of the embedded bootloader. As my system always starts in bootloader mode, this means I cannot start my app.Do you know how to protect the device agains read-out + use STM's embedded bootloader?Kind regards,Jules.#embedded-bootloader #stm32l0 #read-out-protection

Posted on August 22, 2017 at 10:11More specifically we are interested in the AES256-GCM algorithm on STM32F777.Looking at the User Manual (http://www.st.com/content/ccc/resource/technical/document/user_manual/group0/f9/6e/f2/a2/b4/ec/49/c0/DM00215061/files/DM00215061.pdf/jcr:content/translations/en.DM00215061.pdf ) I conclude that for the STM32F756 the crypto hardware is used when using the STM32AccHwCryptoV3.1.0_Xy_C_O.a library.However, if I look at the actual software (library and headers) I get confused:The STM32_Crypto library (not HW accelerated) has a Inc/AES/GCM/aes_gcm.h header.The STM32_Crypto_AccHw variant does not include any header for GCM but Inc/AES/AccHw_aes.h contains the following:&sharpifdef INCLUDE_AccHw_GCM&sharpinclude 'GCM/AccHw_aes_gcm.h'&sharpendifA header with this filename does not ship with the libraries.Does anyone have experience with AES-GCM on a STM32 with crypto accelerator?Best regards,M#aes-256 #crypto #stm32-crypto-lib #stm32f7 #aes

Posted on May 29, 2017 at 21:16I'm trying to use AES with STEVAL-IDB006V1. I'm using some utilities from stm32l1xx_aes_util.c file.I have enabled RCC_AHBPeriph_AES with the command RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE);but when the application tries to execute AES_Init it stops. Taking a look inside AES_Init in stm32l1xx_aes.c file, I have found out the command that stops the app: tmpreg = AES->CR;It seems that AES register is not accessible. Should I enable anything else? What's the problem?#aes #steval-idb006v1

Posted on August 04, 2017 at 11:48Hi,I have a legacy device, a bootloader, running on a STM32F101CBT6.I don't have it's code, so I'm not sure of what's it doing exactly... but I know it locks the flash.My goal is to upload an application, with a payload - my new bootloader, and to flash it to address 0x08000000.I managed to upload my application, but when trying to write (or erase) the flash at 0x08000000, it fails with HAL_FLASH_ERROR_WRP:failed to erase flash, status: 0x1, address: 0x08000000, error: 0x2On a development device, if I try connecting with ST-Link Utility (via ST-Link), I get a pop-up: disable read out protection.How do I overcome the issue, dynamically, from within the application?#read-write-protection

Posted on July 13, 2017 at 18:04Hi all,I am using the STM32L011G3U6 with 8kB FLASH.We deliver this chip programmed with a firmware that is read protected (RDPROT = Level 1)Our customer should be able to write certain data in predefined non-volatile memory (let's say EEPROM) to control certain firmware parameters (for instance, how often a LED blinks).This configuration programming is neither via ST-LINK, my preferred method, nor Bootloader UART commands possible since memory is protected. I cannot separate the code from the program data and then read-protect the 4kB code-sector via WRPi bits in Optional Bytes. My code is 6,5kB with compiler option armcc compiler option set to -O3 (the highest optimization possible).To avoid the former data/code separation there is a compiler option:armcc --no_literal_pools --max_string_in_code=0recommend it inhttp://www.st.com/content/ccc/resource/technical/document/application_note/b4/14/62/81/18/57/48/05/DM00075930.pdf/files/DM00075930.pdf/jcr:conte

Posted on June 27, 2017 at 18:17Hi St communityWe have a custom board based on STM32F429 that runs a gateway application between a wireless transciever and an ethernet link.To check for frames integrity we use a CRC16-CCITT algorithm, each bytes requires several process operations of XOR, shifting ... and the whole operation takes around 330�s to process a 1018 bytes frame.The STM32F429 includes a CRC peripheral, documented in the AN4187 paperhttp://www.st.com/content/ccc/resource/technical/document/application_note/39/89/da/89/9e/d7/49/b1/DM00068118.pdf/files/DM00068118.pdf/jcr:content/translations/en.DM00068118.pdf According to the Table2, the peripheral usage significantly reduced (60 times) the computation time in comparison to an algorithmic implementation.The example used in the paper used the CRC-32 standard and not the CRC-CCITT one.See 'https://www.lammertbies.nl/comm/info/crc-calculation.html Table' or attached PNG for differences.We a

Posted on June 23, 2017 at 04:01Hi everyone!I'm using STM32F105 MCU , and I'd like to explore built-in DFU featureWhen I set BOOT0/BOOT1 pins per datasheet and reboot the MCU, the feature always works ok no matter how read out protection is set in option bitsHowever, jump from application works only if read out protection is offThe jump code disables all IRQ sources used in my application, clears pending interrupts, sets stack top and jumps to system memory per AN2606&sharpdefine _DFU_START (0x1FFFB000) static void (*_p_ldr)(void); NVIC_DisableIRQ(TIM2_IRQn); NVIC_DisableIRQ(TIM3_IRQn); NVIC_DisableIRQ(TIM4_IRQn); NVIC_DisableIRQ(DMA1_Channel1_IRQn); NVIC_ClearPendingIRQ(TIM2_IRQn); NVIC_ClearPendingIRQ(TIM3_IRQn); NVIC_ClearPendingIRQ(TIM4_IRQn); NVIC_ClearPendingIRQ(DMA1_Channel1_IRQn); HAL_RCC_DeInit(); HAL_DeInit(); _p_ldr = ( void(*)(void)) (*((uint32_t *)(_DFU_START+4))); __set_MSP(*(__IO uint32_t*) _DFU_START); _p_ldr();What may cause the problem?#dfu #bootloader #

Posted on June 21, 2017 at 10:14I tried to enable the read out protection on a stm32w108 using stm32 stlink utility. The problem is that the process fails, and I end up having three locked full erased chips. The option byte reports that rdp is enabled, despite the fact that the process failed. I cannot program it, nor change the option byte again. It fails every time. Is there any way to make the mcus functional again ?Is there any other (better) way to avoid someone reading my mcu ?#read-out-protection #stm32 #stm32w #stm32w108

Posted on June 16, 2017 at 12:10Hi,The ProblemI am running uCLinux on the STM32F746. I am using a gadgetfs-based mass storage device with the SD card for a backing file. The USB PHY is an external SMSC ULPI chip. This works fine when connected to most computers, but on some computers it produces errors.Using a LeCroy Mercury T2 USB bus analyser, I have found that in some cases there are CRC errors in the USB packets.When the failed LeCroy USB traces are compared working USB traces, I can see that: both the failed and the good USB packets have the same calculated CRC valuethe data within the failed USB packet has a couple of bits filpped, which is causing the CRC check errorI can replicate this issue on 2 different STM32F746 hardware platforms (with different SMSC USB PHYs), with a variety of cables (some with spec compliant labels), when plugged into some different computers/hubs (high end Dell laptop, hub in a monitor).The Question!uCLinux sets the PLL48CLK as 50MHz. This is out

Posted on July 02, 2015 at 17:53Hello all,I am new to this forum but it has so far been a very good resource for me to learn how to work with the STM32F4 MCU.I have managed to enable RDP Level 1 using software but I was wondering if there was a way to do this using JTAG by directly accessing the registers. I am using Keil's uVision IDE and a J-Link emulator to program my MCU's Flash. When in debug mode, I am able to directly write to registers such as the GPIO_ODR by double clicking and setting the appropriate bits. When I try to do the same to the FLASH_OPTKEYR register to enter the two codes required to unlock the FLASH_OPTCR it does not seem to work. The reason why I am asking this is because I would like to have a technician enable the RDP Lvl 1 without having to change the source code when the cards are being sent out.Thanks!Michael #stm32-rdp-read-protection

Posted on May 12, 2017 at 16:28I found a issue in the latest HAL Libary. * @file    stm32f4xx_hal_hash.h  * @author  MCD Application Team  * @version V1.6.0  * @date    04-November-2016  * @brief   Header file of HASH HAL module.Inside HASH->CR register the mode bit is set for a HMAC calculation.But this bit is never cleared anymore.Therefore It isn't possible to process a HASH calculation with the DMA if a HMAC calculation is done before.I suggest to clear this bit inside HAL_HASH_Init()HASH->CR &= ~HASH_CR_MODE;Or did I miss something?!?**EDIT**It's the same with ALGO mode. After a Md5 calculation it isn't possible to process a SHA-1 calculation anymore.HASH->CR &= ~HASH_CR_ALGO;#issue #stm32 #hash

Posted on April 28, 2017 at 10:40I have two STM32F103 connected together with SPI in full duplex mode. They changing 700 halword with DMA and CRC enabled. The communication is fine (no crc or other error) but there is this line of code in the SPI_DMATransmitReceiveCplt() in the stm32F1xx_hal_spi.c which blocks the code till the SPI_TIMEOUT_VALUE. It is 10 ms. What is the meaning of this blocking? If I change this value to 1 on booth controller it even works fine, but it allways wait till the timeout. I don't want to waste here so many time.May I lower this timeout or set it 0? Or despite the proper CRC there is some kind of error during the communication which cause this hanging?/* CRC Calculation handling */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Check if CRC is done on going (RXNE flag set) */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) { /* Wait until RXNE flag is set to send data */ if(SPI_WaitOnF

Posted on April 22, 2016 at 12:31Hi,I need to implement an existing circa algorithm [1]. I have a table driven C implementation, but I would like to use the STM32L4 CRC peripheral. I�ve read the chapter in the reference manual, and I know which parameters the peripheral allows, but unfortunately, I fail to map them to the �usual� definitions of CRC algorithms. Is there any application note, that describes the �CRC computation� block in more details (I�ve tried to use the st.com-search, but that results just in sql errors)?Any hint on how I would have to map a CRC algorithm with the following parameters to the parameters, the CRC peripheral is using?   bits:       8   poly:       0x9c   init:       0x5a   xor:        0x00   reverse:    false   non-direct: falseThis should result in 0x18 for the test input �123456789� [2]. That�s the code, where I�v

Posted on March 28, 2017 at 12:38 Hi I m using stm32f4 for my project. My project has AES encryption and decryption parts. I using standard peripheral librarys. Standard peripheral library has http://www.hanese.nl/STM32/stm32f4stdlibrary/html/group___c_r_y_p.html. I use this library for AES process. I generate codes like https://github.com/g4lvanix/STM32F4-workarea/blob/master/Project/STM32F4xx_StdPeriph_Examples/CRYP/CRYP_AESmodes/main.c and my codes is following lines. uint8_t AES256key[32] = {0x60,0x3d,0xeb,0x10,0x15,0xca,0x71,0xbe, 0x2b,0x73,0xae,0xf0,0x85,0x7d,0x77,0x81, 0x1f,0x35,0x2c,0x07,0x3b,0x61,0x08,0xd7, 0x2d,0x98,0x10,0xa3,0x09,0x14,0xdf,0xf4}; uint8_t IV_1[16] = {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f}; uint8_t Plaintext[AES_TEXT_SIZE] = {0x6b,0xc1,0xbe,0xe2,0x2e,0x40,0x9f,0x96, 0xe9,0x3d,0x7e,0x11,0x73,0x93,0x17,0x2a, 0xae,0x2d,0x8a,0x57,0x1e,0x03,0xac,0x9c, 0x9e,0xb7,0x6f,0xac,0x45,0xaf,0x8e,0x51, 0x