STM32 MPUs

Due to the high cost of RAM. I wonder if ST have plans or other information about which 4GB RAM vendors fits MP25x products?I know that ST have information about other RAM vendors on their wiki. Only one 4GB vendor is mention there.I bought the 4GB RAM MT53E1G32D2FW-046 WT:C (single rank) from here when it cost 20 USD.https://www.aliexpress.com/item/1005009146059053.html but its seems to only having the DDR density to 8bits (2 GB). Perhaps it was only a 2GB or MT53E1G32D2FW-046 WT:B (dual rank)I'm still looking for other RAM vendors that can offer 4GB solutions for the MP25x. Question:Can ST write a criteria what a RAM memory need to have to fit MP25x? Do the RAM need to follow a specific RAM standard? What do I need to know to know if the RAM memory fits the MP25x? 

Hello, I am using and stm32mp157c-odyssey SoM with a custom made motherboard, However I am having issues getting the usb port function properly.I am using otg fs. It fails the enumeration in the pc side and gets stuck at L1 sometimes and other errors. I still don't know if it's a hardware or software related issues. I am configuring it as device only. below I will include picture of the usb schematic, the logs, as well as the device tree node. Note : We are not using otg_fs_id it's not connected to anythhing , and vbus comes directly from the PC host to the OTG_vbus pin so no vbus gpio.Using yocto image 6.1 mickledore.&usbotg_hs {compatible = "st,stm32mp15-fsotg", "snps,dwc2";status = "okay";pinctrl-names = "default";pinctrl-0 = <&usbotg_fs_dp_dm_pins_a>;dr_mode = "peripheral";};

Hi everyone,I am encountering an issue while trying to flash OpenSTDroid onto my STM32MP257F-DK board.I downloaded the Starter Package from the official website and used STM32CubeProgrammer for the installation. However, the flashing process consistently fails during the final stages.Could anyone provide the correct flashing procedure or suggest what might be causing this error? Below are the details of my setup:Starter Package Source: STM32MP2DroidSta | Product - STMicroelectronicsSTM32CubeProgrammer Error Screenshot:   Thank you in advance for your help!

Hello, I'm trying to install EGit in STM32CubeIDE, but I'm getting an error.Cannot complete the install because one or more required items could not be found. Software being installed: Git integration for Eclipse 7.5.0.202512021534-r (org.eclipse.egit.feature.group 7.5.0.202512021534-r) Missing requirement: Git integration for Eclipse - Core 7.5.0.202512021534-r (org.eclipse.egit.core 7.5.0.202512021534-r) requires 'osgi.bundle; org.eclipse.core.runtime [3.33.100,4.0.0)' but it could not be found Cannot satisfy dependency: From: Git integration for Eclipse 7.5.0.202512021534-r (org.eclipse.egit.feature.group 7.5.0.202512021534-r) To: org.eclipse.equinox.p2.iu; org.eclipse.egit.core [7.5.0.202512021534-r,7.5.0.202512021534-r]Does anyone else have the same problem?

Hello Every One,Hardware / Software EnvironmentBoard: STM32MP257F-EV1Device: STM32MP257FAIxIDE: STM32CubeIDE v2.0.0 (Windows)Firmware package: STM32Cube FW_MP2 v1.2.0OpenSTLinux version: openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11What I DidFlashed OpenSTLinux image to eMMC using USB DFU with:FlashLayout_emmc_stm32mp257f-ev1-ca35tdcid-ostl-optee.tsvFlashing completed successfully.Linux boots correctly and I can log in via UART:root@stm32mp2:~#Created a simple GPIO project for Cortex-M33 using STM32CubeMX and STM32CubeIDE:Selected MCU: STM32MP257FAIx (not board)Selected “M33 Master”Toolchain: STM32CubeIDEProject builds successfully without errorsLinker Memory ConfigurationThe generated linker script places CM33 firmware in DDR memory:NS_VECTOR_TBL : ORIGIN = 0x80100000FLASH : ORIGIN = 0x80100600RAM : ORIGIN = 0x80A00000VIRTIO_SHMEM : ORIGIN = 0x812F8000IPC_SHMEM_1 : ORIGIN = 0x81200000So the CM33 firmware is located in DDR (0x80xxxxxx region).ProblemWhen attempting to debug or download

In my custom FSBL on an STM32MP135AAE3, everything runs great except anytime I try to modify one of the GIC flags it pretty much ignores me completely (when I read it back, my changed bits aren't changed).  I'm guessing this is some kind of trust zone or secure state or similar situation.BTW, when I run my FSBL by setting the chip to serial boot and uploading it that way, it runs great, so I know the code is solid.What do I need to change so my FSBL has full privileges?  Is there a document that talks about this?

Hi!I wonder how I can bypass"Locking RIF conf for peripheral" inside CubeMX.In this case, op-tee is locking peripheral 34, which is the USART6 console output. Hence, that's the last message.I need to unlock peripheral 34. How can I do that?  F/TC:0 0 probe_driver_node:543 Probing stm32-exti on node interrupt-controller@46230000 D/TC:0 0 stm32_exti_rif_parse_dt:423 No global lock on RIF configuration D/TC:0 0 probe_driver_node:556 element: stm32-exti on node interrupt-controller@46230000 deferred 1 time(s) F/TC:0 0 probe_driver_node:543 Probing stm32_gpio-pinctrl on node pinctrl-z@46200000 D/TC:0 0 probe_driver_node:556 element: stm32_gpio-pinctrl on node pinctrl-z@46200000 deferred 1 time(s) F/TC:0 0 probe_driver_node:543 Probing stm32-tamp on node tamp@46010000 D/TC:0 0 probe_driver_node:556 element: stm32-tamp on node tamp@46010000 deferred 1 time(s) F/TC:0 0 probe_driver_node:543 Probing stm32-rtc on node rtc@46000000 D/TC:0 0 probe_driver_node:556 element: stm32

Hello,A question on STM32CubeMX v6.16.1, when  I select OpenAMP in Middleware and Software Packs, I can see configuration options, like COMMUNICATION_MODE, SHM_START_ADDRESS, SHM_SIZE etc, but they are all greyed out and not allowing me to change anything.Is there a way to change these options in STM32CubeMX GUI? (I'm aware that the code generated by CubeMX is cutrrently broken so CubeIDE cannot build this code, and I hope for the fix in the next CubeMX version). Another question - the code in CM33/ folder that is generated by CubeMX, can it be built by the Yocto bitbake, like it does for CA35/ folder?Thanks! Regards,Sergei

Dear ST Community,We are working with the STM32MP257F-EV1 evaluation board and using the Yocto Distribution Package for our software stack.Our intended boot sequence is:Boot starts from the Cortex-M33 core.The M33 firmware is responsible for triggering the boot of the Cortex-A35 core.We would like to confirm:Is this boot flow supported on the STM32MP25x platform?If yes, could you please share the recommended procedure or reference steps to implement this?Any guidance or official documentation links would be greatly appreciated.Thanks and Regards,Ishan

Does the stm32mp157 have an ESV or is there one in progress? 

Hello, everyone! I am trying to program files generated by CubeMX(6.15.0) onto the STM32MP257F-DK.  1. Downloaded the FlashLayout_sdcard_stm32mp257f-dk-optee.tsv in the Starter Package installation folder. 2. When I ran some of the example in the repository using the CubeIDE, I confirmed that they worked normally. (C:\Users\20005\STM32Cube\Repository\STM32Cube_FW_MP2_V1.2.0\Projects\STM32MP257F-DK\Applications\FreeRTOS\FreeRTOS_ThreadCreation)3. Created a file using the CubeMX's Board Selector and modifed only a few configurations.4. Why does this Error window appear? I can't find which settings are wrong.5. I got an error (IAC, SERC)Is there a difference between the example in the repository and how to run the file generated by CubeMX?Attached the CubeMX.ioc file.Please help me. 

Hello,I'm working with the STM32MP257F-DK using the Yocto Project, and I'm trying to enable I2C in my custom Device Tree.However, I’m facing an issue where the I2C controllers remain stuck because of power-domain pending states.Here is the relevant dmesg output showing the problem:It looks like the D1 power domain never reaches sync_state(), which prevents the I2C drivers from probing correctly.I suspect a configuration issue in the power-domain hierarchy or in my SoC/board Device Tree, but I haven’t found the root cause yet.Could someone help me understand what is missing to properly enable the I2C controllers and bring the D1 power domain out of the pending state?Thanks in advance for your support. 

Dear All,I would like to use MYD-LD25X development board, which uses the STM32MP257 I plan to run FreeRTOS on the M33 core and Linux on the A35 cores.Do you know if there are documents that I can follow to run FreeRTOS on M33 core and Linux on the A35 core?  Thank you very much.

Hello everybody.On STM32MP2, is it possible to operate only the M33 like a microcontroller, without booting the A35? Also, if only the M33 is operated, can major peripherals such as I2C and Ethernet be controlled from the M33? (I assume that PCIe would be difficult...)

I am building a custom Yocto image for STM32MP1 (STM32MP157) using ST OpenSTLinux (dunfell-based) and I am facing a persistent U-Boot build failure.Environment:SoC: STM32MP157 (custom board)Yocto: ST OpenSTLinux (dunfell)U-Boot: v2020.10-stm32mp-r2.2Recipe: u-boot-stm32mpMachine: stm32mp1 Issue:During bitbake u-boot-stm32mp, the build fails in do_compile with the following error:.../tmp-glibc/work-shared/stm32mp1/uboot-source is not clean,please run 'make mrproper'This error is triggered by U-Boot’s internal check that aborts when generated files are found in the shared source tree. Observations:The error occurs even after running:bitbake -c clean u-boot-stm32mpThe failure persists until I manually remove:tmp-glibc/work-shared/stm32mp1/uboot-source and then run:bitbake -c cleansstate u-boot-stm32mp At some point earlier, I ran make menuconfig manually in the U-Boot source to inspect SPI configuration, which may have introduced .config or include/config/* into the sh

Hello everyone !device: STM32MP257F-DKWe build the X-LINUX-QT starter package following in steps1.X-LINUX-QT starter packagerepo init -u https://github.com/STMicroelectronics/oe-manifest.git -b refs/tags/openstlinux-6.6-yocto-scarthgap-mpu-v25.06.11 repo sync2.Install X-LINUX-QT distribution package v2.2.0 git clone -b v2.2.0 https://github.com/STMicroelectronics/meta-st-x-linux-qt.git layers/meta-st/meta-st-x-linux-qt git clone -b 6.8.3 https://code.qt.io/yocto/meta-qt6.git layers/meta-qt63.Setup the build environmentDISTRO=openstlinux-weston MACHINE=stm32mp2 BSP_DEPENDENCY="layers/meta-qt6 layers/meta-st/meta-st-x-linux-qt" source layers/meta-st/scripts/envsetup.sh4.building bitbake st-image-qt package-indexthen, we have an error message as follows: Spoiler (Highlight to read)ERROR: qtbase-6.8.3-r0 do_package_qa: QA Issue: /usr/share/examples/corelib/serialization/cbordump/cbortag.py contained in package qtbase-examples requires /usr/usr/bin/env, but no providers found in RDE

Hi ST, How i can I use M33 co-processor of stm32mp257 series , and how can i connected debug with Cubeide,how can i use Ethernet port  through the Co-processor,Note: I am using Opnestlinux distribution package.

I've got an STM32MP135AAE3 for which I'm writing my own FSBL.  It's basically working!There are two scenarios:1) Chip set to serial boot; the BootROM wakes up and I use STM32_Programmer_CLI.exe to send it my FSBL which it stores in SYSRAM, BootROM then passes execution to my FSBL2) Chip set to boot from eMMC; BootROM wakes up, sees my FSBL in eMMC, copies it from eMMC to SYSRAM, passes execution to itIt would be helpful for my FSBL to know which scenario it is, and according to STM32 MPU ROM code overview I should be able to inspect the first 512 bytes SRAM2 for a bunch of boot information as defined in this H file.  It also says SRAM2 is for "ROM code secure data" and SRAM1 is for "ROM code non-secure data" and I'm running in non-secure mode so maybe it's actually SRAM1 for me?In any case, I've got my LD file set up so nobody touches the first 512 bytes of either SRAM1 or SRAM2:MEMORY { SYSRAM (rwx) : ORIGIN = 0x2FFE0000, LENGTH = 128K SRAM1 (rwx) : ORIGIN = 0x3

Hello,unlike the STM32MP157F-DK2 the STM32MP257F-DK is not equipped with an Touch/LCD.Is it possible to use an identical/similar LCD with the STM32MP257F-DK (that means: are the appropriate connections on the board)?Marc

Heyho, until now I have only used the STM32 MCUs, from L01x, to G4,  up to H7 (single core), always bare-metal. We're now thinking about scaling up to some MPU, for more processing power, and also for some faster interfaces (mainly gigabit ethernet). From my first investigations about the MPUs, I'm not sure if we can "afford" this on the personnel side, due to the complexity and very probably the necessity to use an OS (real-time is a must, at least "real" enough for multi-channel low latency audio). We have an overworked software department, and no "embedded SW" people, and I'm more of a hardware designer who can do some basic C stuff. So I'd like to know: which OSs are mostly used on the MPUs, or which are you using how's your experience with these what's the learning curve for newbees anybody working bare-metal with the MPUs, and how's that Thanks in advance!

Linux kernel, Yocto project, etc. each has their LTS strategy, does ST has similar plan for its OpenSTLinux?

I have a STM32MP257F custom board with a MT53E1G32D2FW-046 WT:C (4GB) memory.But when I'm booting the TF-A, then I get this message. Notice that this processor passes the DDR data(stm32mp_ddr_test_data_bus(void)) and DDR rw(stm32mp_ddr_test_rw_access(void)) test! So I don't think that the assembly was bad.ERROR: DDR addr bus test: can't access memory @ 0x100000000 BACKTRACE: START: stm32mp2_ddr_setupThis means that my CPU cannot access the address 0x100000000. This limit is exactly 4GB.If we looking at the code. That means that the offset variable must be 0x80000000, which is 2GB. The function stm32mp_ddr_test_addr_bus(size_t size) is beging called with size = 4294967296 = 4GB.uintptr_t stm32mp_ddr_test_addr_bus(size_t size) { size_t addressmask = size - 1U; size_t offset; size_t testoffset = 0U; /* Write the default pattern at each of the power-of-two offsets. */ for (offset = sizeof(u_register_t); (offset & addressmask) != 0

I am working on STM32MP157F-EV1 and would like your assistance in enabling SPI-NAND support within the OpenSTLinux (Yocto) environment.Overview:Development Board: STM32MP157F-EV1Storage Target: SPI-NAND (Serial NAND)Flash Part Number: GD5F4GM8UEYJGR (GigaDevice, 4 Gbit)Operating System: OpenSTLinux / Yocto-based BSPBoot Objective: Generate a complete bootable image for SPI-NAND (TF-A, U-Boot, Kernel, and RootFS)Currently, the official OpenSTLinux images support eMMC, SD card, NOR, and parallel NAND. However, our design requires SPI-NAND as the primary non-volatile memory. We would like to build and flash the image to SPI-NAND and eventually boot directly from it.Support Requested:Image Generation:How to configure Yocto (OpenSTLinux) to build an image for SPI-NAND on STM32MP157F-EV1?

Hello,I am working on the stm32mp257f-ev1 board and attempting to switch from the default USART2 early crash console output to USART6. I've successfully switch TF-A and U-BOOT console to USART6 but my OP-TEE console continuously outputs on USART2.I've made sure to change the serial0 alias from USART2 to USART6 in the OP-TEE device tree (as I've successfully done in the TF-A device tree) and I've also followed the directions to change the header file stm32mp2_def.h For USART6, I've changed the early crash console in stm32mp2_def.h to the following:#define STM32MP_DEBUG_USART_BASE                    USART6_BASE#define DEBUG_UART_TX_GPIO_BANK_ADDRESS    GPIOF_BASE#define DEBUG_UART_TX_GPIO_BANK_CLK_REG     RCC_GPIOFCFGR#define DEBUG_UART_TX_GPIO_BANK_CLK_EN        RCC_GPIOxCFGR_GPIOxEN#define DEBUG_UART_TX_GPIO_PORT                     

Hi,I am trying to understand and test secure boot on STM32MP1. I was able to compile and boot unsigned tf-a. boot failed as expected as it is not verified.generated keys.Now how to burn these below hash file? can we burn into flash and test without using OTP for development and POC?publicKeyhash.binThank you.