Is it possible to disable 8x division for system clock? Hello,I am bringing up an SPC570S50E1. Using the dev kit I am able to successfully bring up and run some simple code, but I observe a clock division for the clock going into the core.When I route out clockout with a divider of zero and sysclk running from the crystal, I observe a 40 MHz oscillation on the clockout pin. However, when I write assembly code that toggles a GPIO pin every clock cycle, I observe that the clock cycles take 200 ns each, suggesting a 8x clock division happening between the clock stage that the clockout feeds from and the clock stage that the processor core feeds from. (If I run the core from the internal 16 MHz oscillator, I observe the same division behavior). I cannot find any registers or configuration bits in the manual that describe such an 8x clock division. Please let me know if this 8x division is inherent or if there is some way to disable it, so that each clock cycle indeed takes 25 ns. Thank you very much,Anton
