STM32 MCUs

Hello, I am planning out a project that uses new BLE 5.4 feature periodic advertising with response and I wanted to use STM32WBA as a broadcaster and STM32WB0s as observers. There seems to be a great software support for this on WB0 but when it comes to WBA I can't find much documentation or any examples even on periodic advertising. Do you plan to add this in the future? Or is STM3WBA more focused on audio and will not get these features? Thank you

 Hello,I am using an ST7701S LCD over 3-wire SPI (CS, SCK, SDA) with my STM32.When I send the initialization commands from my ESP, I noticed the following:The first command of the sequence is not sent.The program seems to stop at the second stage, around the 100th command.SPI is configured in master mode, polling (no DMA, no interrupts).Example of the write function:void ST7701_Write(uint8_t dc, uint8_t data) { uint16_t value = ((dc & 0x01) << 8) | data; HAL_GPIO_WritePin(LCD_CS_GPIO_Port, LCD_CS_Pin, GPIO_PIN_RESET); HAL_SPI_Transmit(&hspi2, (uint8_t *)&value, 1, HAL_MAX_DELAY); HAL_GPIO_WritePin(LCD_CS_GPIO_Port, LCD_CS_Pin, GPIO_PIN_SET); }Questions:Could the first command being skipped be due to HAL/SPI initialization or state?What is the recommended method to ensure all commands are reliably sent over 3-wire SPI to ST7701S?Thank you for your help.

Hello Everyone,I hope this message finds you well. I am currently developing a USB Host application using the STM32H573I-DK and have encountered a persistent Hard Fault issue that I would like to seek your expertise on.[Environment Information]Target: STM32H573I-DKExample: USBPD_SRC_UX_Host_MSC Stack: Azure RTOS (ThreadX, USBX)[Detailed Symptom]A hard fault occurs during initialization or while driving the process thread (msc_process_thread_entry) when connecting a USB MSC device. Debugging revealed abnormal memory access occurring during execution of the _ux_utility_memory_copy function.[Inquiry]When implementing USBX Host in this example and the STM32H5 environment, we seek broad advice on potential causes that could trigger memory copy and access errors.Example Stability: Are there any known issues or patch histories related to USBX memory management or stack configuration in the currently deployed USBPD_SRC_UX_Host_MSC example?H5 Architecture Characteristics: Are there scenari

I'm using stm32u535 and would like to have zero crossing detection of supply voltage. I've requirement of 6ADC channels and all are configured in differential mode and adc clock is 25Mhz and resolution is 14 bit and dma circular mode is enabled. On channel 6 i e enabled analog watchdog and written logic in isr to toggle GPIO. I proved gpio and I see deviation. Can someone help here. Here is my code snippet:ADC and AWDG initialization: hadc1.Instance = ADC1; hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; hadc1.Init.Resolution = ADC_RESOLUTION_14B; hadc1.Init.GainCompensation = 0; hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; hadc1.Init.EOCSelection = ADC_EOC_SEQ_CONV; hadc1.Init.LowPowerAutoWait = DISABLE; hadc1.Init.ContinuousConvMode = ENABLE; hadc1.Init.NbrOfConversion = 8; hadc1.Init.DiscontinuousConvMode = DISABLE; hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_N

Hi STM Devs!I would like to introduce a thread scheduling library - SuperTinyKernel (STK).Its GitHub repo: https://github.com/dmitrykos/stkYou can check capabilities in detail on GitHub but briefly STK can:Soft and hard real-time support: STK supports cooperative scheduling for “soft real-time” tasks, you can also enable hard real-time mode (KERNEL_HRT) for periodic tasks with guaranteed deadlines.Static and dynamic tasks: Define all tasks at startup (KERNEL_STATIC) or allow tasks to be created and destroyed at runtime (KERNEL_DYNAMIC).Low-power friendliness: STK puts MCU into a low-power mode when there are no runnable tasks (task calls Sleep).Tiny footprint: Minimal C++ abstractions (no STL, no heavy namespaces) keep the kernel small and simple.Portability: Supports ARM Cortex-M and RISC-V RV32 MCUs.Multi-core support: Fully implemented for Cortex-M and RISC-V.x86 development mode: Compile & debug your code on a PC before flashing to the MCU, which helps with early

the best I achieve so far using DWT as well as PMU is 'few cycles' accuracy. My question is, how I measure execution time such that I get 1 cycle difference when I insert a nop in the measured code ? (assuming interrupts and caches are disabled).Both functions below return 1!.global test_pmu0 .type test_pmu0, %function .align 2 test_pmu0: isb sy dsb sy ldr r3, .test_pmu0.pmu_base ldr r0, [r3, #0x7C] //read PMU->CCNTR ldr r1, [r3, #0x7C] //read PMU->CCNTR sub r0,r1,r0 bx lr .align 2 .test_pmu0.pmu_base: .word 0xE0003000 //PMU base address .global test_pmu1 .type test_pmu1, %function .align 2 test_pmu1: isb sy dsb sy ldr r3, .test_pmu1.pmu_base ldr r0, [r3, #0x7C] //read PMU->CCNTR nop ldr r1, [r3, #0x7C] //read PMU->CCNTR sub r0,r1,r0 bx lr .align 2 .test_pmu1.pmu_base: .word 0xE0003000 //PMU base address 

I try to enable the PCROP Feature on a STM32H753I am using the STM32CubeProgrammer and connect via ST-Link V2After connecting, I go to the "OB" page and set the PROT_AREA_END1 value to 0xFFF and activate the DMEP1Then I press the "Apply" button and this happens in the log:Option byte command : -ob PROT_AREA_END1=0xFFF PROGRAMMING OPTION BYTES AREA ... Bank : 0x00 Address : 0x5200201c Size : 308 Bytes UPLOADING OPTION BYTES DATA ... Bank : 0x00 Address : 0x5200201c Size : 308 Bytes OPTION BYTE PROGRAMMING VERIFICATION: Error: Expected value for Option Byte "PROT_AREA_END1": 0xFFF, found: 0x0 Error: Option Byte Programming failedAnd then, I always get the error Message "Option Byte Programming failed"The RDP has level 0, but the same error occures, if I try to set RDP to level 1 at the same time.In the documentation I found no hint, that there is any other prerequisite must be met to set the PCROP.Has anyone an idea what the problem could be?(In generally the chip works, I can eras

Hi everyone,I am encountering an issue with the "Access to MCU Selector" feature.The Problem: After installing X-CUBE-AI packages version 10.2 (or any version later than 10.0), the MCU Selector fails to open. It gets stuck in an infinite loading loop. Additionally, the "Output" view remains empty, showing no error logs.Troubleshooting: I found that if I uninstall the versions newer than 10.0 and revert to X-CUBE-AI version 9.0.0, the MCU Selector works perfectly fine.Has anyone faced this issue? Is there a known workaround or solution to use the 10.2 version without breaking the MCU Selector?Thanks in advance. 

I have a custom PCB with an STM32H563VGT6 microcontroller and an external Winbond W25Q16JVUXIQ NOR flash memory connected to the octoSPI's (XSPI) upper four pins. The problem is I can only write data to the flash memory after an erase, if I reset my board between the two operation. Everything the erasing, writing, indirect reading, memory mapped reading work on their own, but not after erase without reset. I read out all 3 status registers, they are the same before and after the chip erase. (Of course I set the write enable bit before trying to write into the memory) Any idea what could be the problem?

I want to design a baord with stm32h7b0zbt6 with extranal sdram chip W9825G6KH-6. I get PG15 with FMC_SDNCAS alt func in datasheet as below:But when I looked the PG15 alt func config I get as below info, I could not found an alternate function number for FMC_SDNCAS here ?? why they are not consistent ? 

From cube 1.3.0 I always get this error and the cause seems to be the path generation in .d files. In cube 1.12.1 the path is relative but from cube 1.3.0 it is absolute and generates something like \\?\C:\.... So the only solution for me is to stay with cube 1.12.0. The build however seems ok an the bin file is generated. Did anyone had a similar issue? The issue is present only on windows and it seems ok on linux.arm-none-eabi-size STM32F769I_TEST.elfarm-none-eabi-objdump -h -S STM32F769I_TEST.elf > "STM32F769I_TEST.list"arm-none-eabi-objcopy -O ihex STM32F769I_TEST.elf "STM32F769I_TEST.hex"arm-none-eabi-objcopy -O binary STM32F769I_TEST.elf "STM32F769I_TEST.bin"text data bss dec hex filename1227608 43680 452264 1723552 1a4ca0 STM32F769I_TEST.elfFinished building: default.size.stdoutFinished building: STM32F769I_TEST.hexFinished building: STM32F769I_TEST.binFinished building: STM32F769I_TEST.listtest/web/unicabminnow.d:1: *** multiple target patterns. Stop.make: *** [makefile

Hi there, i hope youre doing great! Im exploring FUOTA over LoRa/LoRaWAN using STM32CubeWL and the Nucleo-WL55JC1For this purpose im exploring the application (included in STM32CubeWL) "LoRaWAN_FUOTA_DualCore"I read the 'readme' file to accomplish build and flashing of the board with this application but the build.bat file throws an errorSo i decided to compile every project of the full application inside STM32CubeIDE, but in the project 'LoRaWAN_End_Node_DualCore_CM0PLUS' i found a linker error:... LoRaWAN_End_Node_DualCore_CM0PLUS.elf section `.data' will not fit in region `APPLI_ROM'...region `APPLI_ROM' overflowed by 272 bytesIm using STM32CubeIDE v2.0.0 and STM32CubeWL v1.4.0, running on windows 11Am i doing something wrong? Any suggestions?

Hello,Description: I am attempting to generate two simultaneous pulses of different lengths using a single timer (TIM4) and multiple channels.Current Implementation: I am currently using One-Pulse Mode (OPM). In my existing setup, the pulse starts at CCR and ends at ARR. However, since ARR is a global register for the timer, all channels are constrained to the same end time, making it impossible to achieve independent pulse widths if they all trigger at the same ARR event.Objective: To achieve independent pulse widths, I want the pulse to start at CNT = 0 and end at CNT = CCRx for each channel. This would allow CCR1 and CCR2 to define the lengths independently while sharing the same timer base.The Problem: I am struggling to maintain the correct output state outside of the pulse window (specifically for t<0 and t>ARR). I have attempted to use LL_TIM_OCMODE_FORCED_INACTIVE to keep the pin low before the trigger and then switch to LL_TIM_OCMODE_PWM1 just before enabling the counter

NUCLEO-F411REI have ADC1 to DMA in a circular buffer 4 samples long (ADC_VAL). I then use a TIM1 interrupt to send the contents via UART to a PC. int16_t ADC_VAL[4]; ... HAL_ADC_STart_DMA(&hadc1, (uint32_t *)ADC_VAL, 4); /* TIM1 callback */ void HAL_TIM_periodElapsedCallback(TIM_HandleTypeDef *htim) { HAL_UART_Transmit(&huart2, (uint8_t *)ADC_VAL, 16, 10); }   Should I have declared ADC_VAL as a uint32_t ?  

Does the STM32N6570-DK board support XSPI/OSPI interfaces for communication with external peripherals, or are these interfaces limited only to internal or external memory devices?For example, if there is a Device that supports OSPI/XSPI for communication, is it possible to connect the STM32N6570-DK board to such a device to enable data exchange?Could you please provide a clear explanation of the capabilities and practical use cases of the OSPI/XSPI interface on the STM32N6570-DK board?

I have enrolled the gateway and the end node of my PNUCLEO lrwan 3 on Loriot server, but when I view the boot log on my Terra Term terminal, I observe that the end node does not join the server, returning JOINED FAILED.I made sure the end node and the gateway are configured to the same frequency - EU433I also made sure I used the correct details like the dev EUI, APP EUI amd AppKey from the end node to connect to the server, what could be the cause of this JOIN FAILED.

I am trying to get the CAN Loopback up and running on my STM32L431KCU (CAN1), I have tried to follow the: Guide to CAN (bxCAN/CAN2.0) configuration in Loop back mode on STM32 MCUs. But I am getting stuck in the "HAL_CAN_Start()" function where its waiting for the acknowledgement:  /* Wait the acknowledge */ while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) { /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { /* Update error code */ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; return HAL_ERROR; } } I then created a new project following the CAN loopback project listed here to get a working project and around my issue: Solved: CAN bus doesn't work in loopback mode - STMicroelectronics Community Using the same MX CAN config, APB1 of 80MHz, example program, and I still run into being stuck in the "HAL_CAN_Start()". I am using STM32CubeIDE 2.0

Hello,here the exit of my (extended)initialization prodecure for ADC of STM32U535 running at 3.3v and 160 Mhz.  Before setting ADC_CR_ADSTART, without the small delay or with the delay in line 14  and the limit for i smaller "6" like here "5" in the code, ADC_CR_ADSTART stays high  and the programm keeps in the while (ADC1->CR & ADC_CR_ADSTART)  loop line16/17. __DMB() is not replacement for the delay.Is the needed delay some artefact of my setup or some requirement that I do not find/oversee in RM0456? ADC1->CR |= ADC_CR_ADCAL; /*8*/ while (ADC1->CR & ADC_CR_ADCAL) { __NOP(); } __DMB(); ADC1->CR &= ~ADC_CR_ADCALLIN; __DMB(); const uint8_t channel = 19U; AdcSetRegularSequence(ADC1, 1U, &channel); ADC1->CR |= ADC_CR_ADEN; while (!(ADC1->ISR & ADC_ISR_ADRDY)) { __NOP(); } for (volatile int i = 0; i < 5; i++) {} ADC1->CR |= ADC_CR_ADSTART; while (ADC1->CR & ADC_CR_ADSTART) { __NOP();  

Hi all, our product, used in industrial traction, uses an STM32F407 MCU. In certain conditions, very hard to replicate, the MCU stucks and the watchdog does not reset the MCU. It seems completely blocked.  We're suspecting there are some EMC issue on certain brushed motors used the truck but it is not under our control.   After we remove the power supply of the board and give back the supply, the board starts to work again. Someone suggest me some latchup phenomena and I think it could be a possible explanation. Now: how can I find what is the pin (or what are the pins) susceptible to the EMI? There could be some traces the phenomena leaves on the MCU?  Thanks!

Hello all,We are testing LPUART wake-up from Stop 2 mode using the STM32CubeU0 LL example:STM32Cube_FW_U0_V1.2.0/Projects/NUCLEOU083RC/Examples_LL/LPUART/LPUART_WakeUpFromStop2_InitWe made a minimal modification to the example:Replaced LPUART1 with LPUART2 Used the corresponding GPIO pins for LPUART2 (PB10,PB11)Configuration otherwise unchanged (same clock source, wake-up on RX, interrupt-based RX)Observed behavior on NUCLEO-U083RCAfter programming the board using STM32CubeProgrammer in hardware reset mode, the example works correctly:MCU enters Stop 2RX activity on LPUART2 wakes the system as expectedHowever, after disconnecting and reconnecting the power supply LPUART2 no longer wakes the MCU from Stop 2RX data arrives on the pin, but no wake-up occursIf we again connect and disconnect the programmer (in hardware reset mode) the system starts working normally again, wake-up from Stop 2 via LPUART2 is restoredAdditional observationsUsing LPUART1 instead of LPUART2,

Hello ST team,I am studying the flash security mechanisms (RDP, WRP, PCROP) on STM32L476RG and I understand how to configure Option Bytes using STM32CubeProgrammer or firmware.What I am trying to understand is the hardware-level enforcement flow of Option Bytes:• During reset / power-up, which hardware blocks read the Option Bytes?• How are these values propagated to the Flash controller and debug access logic?• At what point relative to CPU reset release are these protections enforced?I understand that enforcement happens before user firmware execution, but the reference manual does not describe the internal sequence in detail.Could you please clarify (at a high level) how Option Bytes are latched and enforced by hardware during the boot/reset sequence on STM32L4 devices?Thank you.

I just installed CubeIDE 2.0.0 on Ubuntu 24.04 (finally!).  However I cannot launch it (I do get the initial workspace selection popup, but after selecting "Launch" I get this error):$ /opt/st/stm32cubeide_2.0.0/stm32cubeide_wayland Could not create GBM EGL display: EGL_NOT_INITIALIZED. Aborting...A little bit of poking around on Google suggests that installing libnvidia-egl-wayland1 should fix this issue, however on my system libnvidia-egl-wayland1 is already installed:$ dpkg -l | grep libnvidia-egl-wayland1ii libnvidia-egl-wayland1:amd64 1:1.1.13-1ubuntu0.1 amd64 Wayland EGL External Platform library -- shared libraryii libnvidia-egl-wayland1:i386 1:1.1.13-1ubuntu0.1 i386 Wayland EGL External Platform library -- shared library I have tried rebooting a couple of times but I keep getting the same error.  Does anyone know how to fix this?

SOMETIMES (not always), when i try to debug (and only when i try to debug, run does its job well) with STM32CubeIDE my Riverdi board, i encounter the "Could not verify ST device! Please verify that the last version of the GDB-server is used for the connection" error. It happens right afterLoading RTOS driver... ThreadXConnecting to GDB server 127.0.0.1 on port 61234 ... ConnectedListen for GDB connection on port: 60000 ... Connected.if this helps.Downloading code with run is always fine, and sometimes the debug option works, but not always. It is really annoying to rely on luck to make the *** thing work. I tried unplug-replug. The board is definitly not counterfeited, same goes for the ST-Link. 

I made a support pack for better support of CAN connections.But there is no possibility to create a "Platform Setting" for CAN connections I tried to edit the "Modes.xml" manually. Than the PackCreator shows the correct IP, but STM32CubeMX doesn't accept it.  Additional: if I create a not usable platform setting there will be "unsovlable" warning.

I am using STM32H753ZI and trying to bring up Ethernet (LAN8742, RMII) using HAL + lwIP in NO-RTOS  mode. I generated the code using STM32CubeMX with ETH enabled (RMII) and lwIP enabled (WITH_RTOS disabled, static IP). The PHY link comes up and RJ45 LEDs blink, but the board does not respond to ping and no ARP entry is created on the PC (Destination Host Unreachable). I have placed ETH descriptors and RX buffers in D2 SRAM, enabled MPU and D-Cache, verified RMII_REF_CLK to PA1, selected the LAN8742 PHY driver, and I am calling MX_ETH_Init(), MX_LWIP_Init(), and processing lwIP in the main loop. The FreeRTOS-based STM32H743 Ethernet example works, but I specifically want a HAL-only .