STM32 MCUs Products

Hello Team,We are developing custom board using STM32N657X0H3Q MCU. I could not find information regarding GPIO status in datasheet during boot mode, sleep mode, stop mode and standby mode. It will be helpful for us if you can share information with us.Thanks

Hi everyone,I’m exploring how embedded systems and modern digital platforms are evolving together, especially in terms of user interaction and performance optimization.It’s interesting to see how both hardware (like STM32 MCUs) and software platforms focus on efficiency, speed, and user experience.In a broader digital context, many platforms are also improving how users engage and interact online through optimized systems and interfaces.Looking forward to learning more from this community.

Hello dear community!I've migrated from F7 to H7, everything fine so far.To save CPU time I don't want to use HAL for sending two SPI bytes.My F7 transmit SPI code was very simple and perfectly working :SPI6->DR = byte_0; SPI6->DR = byte_1;But on the H7, the same code doesn't work :SPI6->TXDR = byte_0; SPI6->TXDR = byte_1;In both F7 and H7 projects, this is always working (but time-consuming) :HAL_SPI_Transmit(&hspi6, const_cast<uint8_t*>(buffer), 2, 1000);Do you know why bypassing HAL is not possible on the H7 ?Thanks!Jean

Hello All,I am working on a custom project using STM32C011J6/SO8.I was trying to use PIN4 as ADC with 3 differents states but once I connect to GND, mcu resets. So now, I have no access to the mcu via Debugger because I set NRST_MODE in Option bytes to : 0x10 only internal RESET is possible.My questions:- Is there a way to recover it knowing that I tested and I can't access system memory.- I am using all the 6 pins (4 ADCs and 2 Outputs). Can I use the PIN4/PA0 as ouput without having reset issues?I know I can still block the reset by Option bytes but I am not sure if I would need a FW change in the future.Thanks,Ayoub

Hello, Is it possible to use two OSPI with below configuration.  I can make this configuration in cubeMx but whiel debugging ospi1 is not working after ospi2 initialize.   

Hello Team,We are using the internal SMPS configuration for the core power supply. However, the power-up sequence does not specify the timing requirements for the different stages.Could you please provide the timing details for the following? What should be the time duration for the PWR_ON signal to transition from low to high while VDD and VDDA18AON are rising (Step 1)?After PWR_ON goes high, what is the required time duration for VDDA18PMU / VDDSMPS to rise (Step 2)?What is the exact meaning and function of the SDEN signal?Are there any additional considerations or recommended guidelines to be followed during the power-up and power-down sequence? Thanks 

Goal boot from a Quad SPI flashI shouldn't need to change any OTP settings.  Any sNor flash chip connected to XSPIM_P2 that can operated in single spi mode can be booted off from? From my understanding if we want to make a dev board and use a different external memory that is not Octo SPI flash but just Quad SPI flash we shouldn't have to change any of the OTP registers.  SinceIn sNor flash it starts in single spi modeThen in your FSB you can configure the SPI to your given device(From my understanding)There are no OTP registers for Nor flash settingsThese are all setup in the ROMChanging OTP 11 bits (5-8) would force us to loose the ability of Dev up (From my understanding) Most of this info is from theHow to proceed with boot ROM on STM32N6 MCUshttps://www.st.com/resource/en/user_manual/um3234-how-to-proceed-with-boot-rom-on-stm32n6-mcus-stmicroelectronics.pdf  No boot source is programmed in OTP default source is serial NOR No configurati

Hi all.I'm new to STM, but have been designing and making embedded MCU products for over ten years.I was drawn to the STM32F105 series because of the USB DFU, to allow for field updates for prospective customers to update a product we're developing. Outside of USB DFU functionality, we just need 3x UART's, one GPI, one GPO. That's it. We steer clear of USART1 because of it's overlap with OTG_FS pins. We have got our product working using a ST-Link programmer, but not as yet using the USB DFU.Our USB connection just isn't enumerating. The wiring is correct when compared to off-the-shelf STM32 enabled boards with OTG USB interfaces.I am across the date code bootloader issue as described in AN2606, our chips definitely come with bootloader 2.2. I have VBUS from the USB-C tied to PA9 (OTG_FS_VBUS). Yes, USB-C but with the 5.1K resistors between CC1, CC2 and GND. NRST is pulled to 3V3 with a 10K pull-up. Boot0 and Boot1 is pulled to GND via a 10K pull-down, Boot0 also runs to a tactile NO p

i have a tool base website that made by Claude/cursor ai. but now the issue is the color scheming is not very good it looks that it made by vibe coding. suggest some good color scheming and layout that make difference and looks more professional and human made CPU Bottleneck

The entry for address 0x1FFF7838 in Table 17 ( Organization of option bytes) shows FLASH_PCROP1ASR as the "Corresponding option register" - it should be FLASH_PCROP2ASR.

While I was experimenting with the 'L476 Disco, the RM wording goes across multiple families, so it may be relevant to most/all of them. In particular, for Shutdown mode (which is supposedly the lowest-VDD-consumption mode), the RM says: What does "switch to Backup domain is not supported" mean, exactly (assuming VDD and VBAT have separate sources)?  as soon as Shutdown mode is entered, RTC (backup domain) is switched to VBAT even if VDD is present, potentially draining the VBAT source (battery, capacitor) in Shutdown, while VDD is present, RTC is powered from VDD; but when VDD is removed, RTC is *not* switched to VBAT, resulting in backup-domain reset and/or RTC corruption in Shutdown, while VDD is present, RTC is powered from VDD; but when VDD is removed, most of the time the switch flips to VBAT as expected, but this is not reliable and sometimes RTC corruption occurs in Shutdown, it's unpredictible, what is the backup-domain switch state, even while VDD is present These are

I’m designing a board using the STM32U083MCT6TR, and my system supply voltage is VDD = 1.8 V.The design does not use USB at all. The datasheet specifies that VDDUSB normally requires 3.0–3.6 V for USB operation, but it’s not fully clear what the correct connection is when USB functionality is not needed. My question:What is the recommended way to handle the VDDUSB pin when USB is unused and the MCU is powered at 1.8 V? Should VDDUSB be tied to VDD (1.8 V)? Should it be left unconnected? Or is another configuration required? If anyone has experience with the STM32U0 series or clarification from ST, I’d appreciate the guidance. Thanks, -Tal

Split from WiFi or WiFi+BT modules architecture and parts recommendations as that's really a separate question!Thank you @Andrew Neil I didn’t explain myself very clearly. The part I’m mainly interested in is the audio side — specifically, a microcontroller with some kind of audio I/O capability, such as microphone input and speaker output, for recording (and then saving to uSD - perhaps using DMA if it makes sense). I’ve never worked with microcontrollers for audio recording before, so if such micro is not available, I’m also open to a low-cost solution/architecture that uses external components.Thank you

(I tried to submit a ticket but the system seems broken, giving an obscure error about an incorrect zip code).I need to confirm which version of STM32 is placed on a board. There are two versions, GP and PD. The datasheet does not really specify how the top marking is different for the two versions.    Any ideas?Thanks, Pete

Hello, in the STM32H753xI datasheet, Table 11, "Total current into sum of all VDD power lines (620mA)," is the voltage condition VDD = 3.3V? I would also like to know the current at VDD = 1.8V.

I have a project that is using custom hardware with a STM32G0B1CBT6 processor.  The code is developed using STM32CubeIDE and STM32CubeMX.  However, there are times when I am unable to run a debug session and I'm seeing (very) occasional Hard Faults.I have a diagnostic serial port and have successfully modified my Hard Fault Handler to dump additional information out that port.So what I'm after is some code that can read registers and/or the stack to provide additional information that I can use (along with the map file, etc) to determine where my Hard Fault is happening.Can anyone point me in the right direction?  All my searches have shown me code that references registers I can't seem to find in the docs.Thanks.  

:warning:Note: The internal GPIO structure has been simplified for better conceptual understanding. (Components such as ESD protection diodes, pull-up and pull-down resistors, etc., are not shown.):warning:Warning / Disclaimer This analysis is based on my personal study and interpretation of technical documents. Therefore, I cannot guarantee that it fully represents the actual internal behavior of all STM32 microcontrollers. This is a simplified conceptual model for educational purposes. INTRODUCTION In this document, we will examine how our code affects GPIO units at the MOSFET level. Our analysis focuses on the MOSFET switching logic in General Purpose Output (Push-Pull, Open-Drain) and Input Mode (Analog and Alternate Function modes are not included in this analysis). I used the following documents as references for this analysis and the visuals: AN4899 Application Note (STMicroelectronics) RM0365 Reference Manual (STM32F3 series) Since this analysis is based on the STM32 archite

STM32C092CCT6 : TCAN1463-Q1: TXD Dominant but No CAN Output — Bit0 Errors, nFAULT OK, Normal Mode Confirmed Hello everyone,I am facing an issue where the CAN transceiver (TCAN1463-Q1) does not drive the CAN bus even though the STM32 FDCAN peripheral is transmitting correctly and the transceiver is confirmed to be in Normal mode. Hardware SetupNode 1 — STM32 Daughter Board (Transmitter)MCU: STM32C092CCT6 (Cortex-M0+, 12 MHz SYSCLK)Transceiver: TCAN1463-Q1Connections:TXD → PB1 (FDCAN1_TX, AF3, Very High Speed)RXD → PB0 (FDCAN1_RX, AF3)EN → PC6 (HIGH = enabled)nSTB → PB12 via hardware inverterPB12 HIGH → nSTB HIGH → Normal modenFAULT → PC7 (active-low, pull-up to 3.3V)Power:VSUP = 5VVIO = 3.3VNode 2 — ReceiverRaspberry Pi CM4 + MCP2518FD (SPI, 40 MHz crystal)TCAN1463-Q1SocketCAN interfaceBoth nodes are connected with proper 120Ω termination.FDCAN ConfigurationClassic CAN (1 Mbps)FrameFormat = Classic CANClock = 12 MHz (PCLK1)Prescaler = 1TSEG1 = 8TSEG2 = 3Sample Point = 75%Proto

Hi,we would like to add live video playing/streaming to an STM32-based board we are designing that uses MIPI-DSI to drive a touch display, and we are at the stage of choosing the micro.Ideally it would stream from HDMI signal but we can use another interface if more suitable and/or lower cost.(Ethernet streaming I think is just a matter of having the Ethernet connection so that I assume is straight forward).The live video would be played on the touch display but in a window slightly smaller than the graphic area (to allow controls for other electronics to be places on the graphical area next to the video).Are there any STM32 that have perhaps some special dedicated hardware to allow video streaming (again from HDMI or other similar inputs) while preventing major core bottleneck/slow-down?If so, which micro can do that?Or which peripherals/HW of the STM32 is used to do that so we can select the right micro?Thank you. :)

Post edited by a ST moderator: 1- Translate the text to English. 2- Update the title to be more concise. 3- Update the label.   我在使用STM32G070系列芯片时，外部电阻上拉到3.3V，接入STM32芯片后测量，发现GPIOA 15 和GPIO A8两个引脚是0.9V的电压，为什么？ Translation: "When using the STM32G070 series chip, I pulled the external resistor up to 3.3V. After connecting it to the STM32 chip, I measured the voltage on the GPIOA 15 and GPIO A8 pins and found that they were 0.9V. Why is that?"

Dear ST We are currently proceeding with development using the STM32H743VGT6.As you can see in the datasheet, the STM32H743VGT6 has a built-in 1M flash.I confirmed that it operates normally even though the flash partition was divided as shown below for the FOTA function.and Confirmed normal operation of arbitrary 0xFFFF0F0 Write/Read at address 0x8140030 in the Storage area. Therefore, to check if the MCU with 2MB Flash was incorrectly mounted on the PCB, I disassembled the device and examined the STM MCU part number under a microscope, confirming that it is an STM32H743VGT6 as shown in the figure belowAnd by referring to the RM04033 reference manual and reading the flash size as shown below, I confirmed that it has 1MB of Flash.The register values ​​and product name on the STM32H743VGT6 appear to indicate a 1MB FLASH, so I am wondering why READ & WRITE to the FLASH is working normally even in areas exceeding 1MBThanksBRMr.shim  

Hello everyone, I am using the NUCLEO-H755ZI-Q board for a project. I have noticed that the HRTIMs thatare not multiplexed with some USB pins (like the HRTIM_D1 with the D+ for programming the IC via usb)work normally, while if they do, I can't output any PWM pulse. Is this actually a thing and to overcome itI have to remove some of the Zero Ohm resistors behind the nucleo board or design a custom pcb for my needsor am I messing something up? In my situation specifically, i can output from all HRTIM channels except the D1and D2, both of which map to a pin with USB. Thanks in advance! 

Hello Peter ,  Need your expert reply  As we see , the confusion on N AND no N HAS MADE many of us wonder , if these can be used as  interchangeable parts . Since Data Sheet does not explain , much on them ,But a search explains a compact Solution in Io's for a design flexibility .  As both have same Packages and Pin  Count .  We are in need for DESIGN - STM32G0B1CBT3N , but seems to be difficult  to procure  . Is this Manufactured or is it rare . We only See STM32G0B1CBT6N    Regards Nitin

hello ST Community, I need your support. So far, I've been able to flash my bootloader software into the unprotected memory area 0x08000000 when Boot0 = 0 for the NUCLEO-H755ZI-Q series, both with the STM32CubeProgrammer and with my bootloader software via UART. However, I'd like to flash the same bootloader software into the memory area 0x1ff00000 when Boot0 = 1. I know it's protected. Is it possible to change the security level or flash it to another memory to run my software when Boot0 = 1? Thank you for your support.

Only 2 of 4 QSPI data lines active during pixel write, despite DMODE=3 confirmed in CCR 이미지 4장을 모두 참조하여 ST Community 문의 글을 작성합니다.EnvironmentMCU: STM32U5G9ZJ (Cortex-M33, TrustZone enabled)IDE: STM32CubeIDEHAL version: STM32U5xx HAL Driver (included in project)Interface: HSPI1 → QSPI LCD (ICNA3306-compatible controller) Hardware ConfigurationGPIO settings are shown in [XSPI_2.png]. All six HSPI1 pins are configured as Alternate Function Push-Pull with GPIO_SPEED_FREQ_VERY_HIGH and GPIO_AF8_HSPI1:Pin Signal Speed PI3HSPI1_CLKVery HighPH9HSPI1_NCSVery HighPH10HSPI1_IO0Very HighPH11HSPI1_IO1Very HighPH12HSPI1_IO2Very HighPH13HSPI1_IO3Very HighClock configuration is shown in [XSPI_3.png]: HSPI1 kernel clock source is set to SYSCLK (160 MHz). PLL1: HSE(16MHz) × PLLN(10) / PLLR(1) = 160 MHz.CubeMX parameter settings are shown in [XSPI_1.png]:Fifo Threshold: 4 bytesMemory Type: MicronClock Prescaler: 1 (→ FCLK = 80 MHz)Clock Mode: Low (Mode 0)Sample Shifting: Half Cycle Problem