STM32 MCUs Products

Hi.I made a custom board using stm32f767connect Coincell (CR1220) to VBAT and turn it off, I think I'm going into some modeSometimes it does not go into the main when the power is turned on again, and the battery life is short when the power is turned offHow can I solve this problem?

Hi everyone can you Please help me to solve this problem,In stm32mp1, Modbus RTU HW handshake communication is not established after Timeout,So after timeout try to reconnect againCTS line is always highCTSIF SR is getting set,Busy flag is set,And RTOF Flag is Not detected.And communication is not going to established. Due to this issue my project got stuck, Kindly provide solution.

Hi all,I was trying to write to the codec (WM8994) I2C3 in the STM32F746 Disco board without luck. After trying a few things and looking at the data on my scope I realized the codec was not acknowledging the address. The problem is I was using 0x68 (for writting) for the address. The 7-bit address is 0x34 and this is what worked. I left shifted it because when I read UM1905 (Description of STM32F7 HAL and low-layer drivers, bottom of page 494 picture below) it says to left shift the address before calling the interface. I'm confused. What does the "The device 7 bits address value in datasheet must be shifted to the left before calling the interface" means? Thanks. 

STM says: OCTOSPI can generate a "regular SPI" transaction. But is not true:A "regular SPI transaction" means actually on OCTOSPI: a half-duplex SPI transaction (using just IO0, but for both directions).I you want to generate a "regular" SPI transactions, as full-duplex ! (IO0 = MOSI, IO1 = MISO, bi-directional) - it is NOT possible.OCTOSPI cannot do WRITE and READ at the same time (always just half-duplex), And the pins for OCTOSPI are NOT shared with a "regular SPI device" (like SPI1, SPI2, SPI3).Here is a solution:run the OCTOSPI as a SPI Master (only as TX, bits out on IO0 pin as MOSI)configure another "regular SPI" device, e.g. SPI3, as a SPI3 Slave (in NCS SW mode: just connect SCK and receive via SPI3 MOSI: connect with IO1 on QSPI he

Hi, when configure MCU to deep sleep mode as the low power mode, it seems okay when debugging. But, when only power up STM32C0 by just connected its vcc and ground, it do not enter its interrupt. How can I solve it?My project goals are to achieve lowest current consumption and MCU able to communication with other modules through I2C and USART. Those communication protocols are triggered by its interrupt using timer1.int main(void){  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */HAL_Init();   /* Configure the system clock */  SystemClock_Config();   /* Initialize all configured peripherals */  MX_GPIO_Init();  MX_TIM1_Init();  MX_I2C1_Init();  MX_USART1_UART_Init();  /* USER CODE BEGIN 2 */  LPS_Init();

"I used the STM32F746ZG to read the current from an ACS712 sensor, but the problem is that the ADC is not stable. I tried using an STM32F466RE to measure the same current, and this time the ADC is stable. I don't understand why, despite the ADC characteristics of the two STM32 being similar. Is there an explanation for this?"please see the two images below

I've tried to see if I can get away with using just one bank address pin for a 4-bank SDRAM (IS42/45S16160J). My understanding is that this would half the addressable memory, as I could only access two banks instead of four.In the STM32H7 user manual I find the following table that matches my SDRAM:This indicates to me that the banks are laid out as contiguous memory blocks.However, when I try this by configuring BA1 as GPIO output and set it to either low or high, I find that I can access the whole memory but only using 1- or 2-byte access, while 4-byte access are not working anymore (atleast not on 0xd0000000). It also doesn't seem to matter how I init th

Hello everyone,I intend to migrate an LPC development to the new stm32h5 family, I find the versatility that its flash offers very interesting. Being able to separate a set of memory into two blocks to run the main program without the need for an IAP firmware. but I have doubts.In my old LPC I had an EEPROM memory clearly separated from the memory block. In the new stm32h5 there is talk of a high-cycling Flash capability that can function as a kind of EEPROM. My question is, can I dedicate the bank 1 portion of the Flash to EEPROM emulation and still maintain the ability to swap between banks for software updates?Thanks in advance!Victor

Using the STM32H747I-DISCO, I am having problems getting SPI working at all.I am using SPI5, to allow connecting an X-NUCLEO-NFC08A1 directly via the Arduino headers.I do not see any data on the SCK line and HAL_SPI_Transmit() always fails.Looking in stm32h7xx_hal_spi.c, I see that SPI_FLAG_EOT is never detected and so HAL_SPI_Transmit() times out with HAL_SPI_ERROR_FLAG set.Is there a working sample showing SPI configuration and use on the STM32H747?Can anyone suggest what I'm doing wrong?Thanks.Pin/port definitions:#define SPIx SPI5 #define SPIx_IRQn SPI5_IRQn #define SPIx_SCK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOK_CLK_ENABLE() #define SPIx_MISO_GPIO_CLK_ENABLE() __HAL_RCC_GPIOJ_CLK_ENABLE() #define SPIx_MOSI_GPIO_CLK_ENABLE() __HAL_RCC_GPIOJ_CLK_ENABLE() #define SPIx_CLK_ENABLE() __HAL_RCC_SPI5_CLK_ENABLE() #define SPIx_SCK_PIN 0 #define SPIx_SCK_GPIO_PORT GPIOK #define SPIx_SCK_AF GPI

Hello everyone,we are developing a product using STM32F413.We got a new requirement, that the chip needs to activate ROP level 1. We want to do this from firmware code, if possible.I noticed that after flashing my firmware and running the code that activates the ROP, the mcu stops working until i perform a power on reset. The ROP is set to level 1 after the power on reset, as expected. The need for the power on reset seems to be caused by not having a power on reset between using the programmer and setting the ROP level. Problem is, that we have a huge super-cap on the board, buffering the power, so a power on reset is out of the picture for production.I know that for STM32L0x3, there was a way around this by performing a wakeup from standby instead of a POR. I had no luck implementing the same for STM32F413. Is there any way to set the ROP from a just flashed firmware without doing a power on reset? From RM0367 Rev8 chapter 3.4 (stm32l

I'm finding difficult to get the value from the channel that i configured of a regular channel with stm32l412 microcontroller. where I'm not getting the EOC interrupt enabled in ADC_ISR register.  and When I tried to get data from ADC_CDR register, it throwing error on me like there no like this register is exists. Really not understood why is happening like this. Please help me in this.

Hi,I have the following board : NUCLEO-F429ZIThe datasheet says that UART3 is the STLINK UART that can be used over USB.I configured this UART but when I try to receive anything from the terminal that is connected to the UART com port, I don't see the interrupt being triggered.The objective is to receive some data over UART3, process it, and send the processed data over UART6.UART3 init in main.c/** * @brief USART3 Initialization Function * @PAram None * @retval None */ static void MX_USART3_UART_Init(void) { /* USER CODE BEGIN USART3_Init 0 */ /* USER CODE END USART3_Init 0 */ /* USER CODE BEGIN USART3_Init 1 */ /* USER CODE END USART3_Init 1 */ huart3.Instance = USART3; huart3.Init.BaudRate = 115200; huart3.Init.WordLength = UART_WORDLENGTH_8B; huart3.Init.StopBits = UART_STOP

In an STM32F427, according to the Backup domain reset subchapter of RCC chapter of RM0090rev.19, backup domain can be reset by setting RCC_BDCR.BDRST. There is no other condition to this mentioned in that subchapter nor elsewhere in related material (e.g. in description of RCC_BDCR.BDRST bit) in the RM.However, experimentally I found, that backup domain reset does not happen after setting RCC_BDCR.BDRST, if PWR_CR.DBP is not set.JW

Hi, i'm dealing with fdcan and have problems with high speeds, 1Mbps works good, but 8Mbps (which works in loopback mode) doesn't, I tried with delay compensation, but didn't work, or maybe i used it wrong way? static void MX_FDCAN1_Init(void){ /* USER CODE BEGIN FDCAN1_Init 0 */ /* USER CODE END FDCAN1_Init 0 */ /* USER CODE BEGIN FDCAN1_Init 1 */ /* USER CODE END FDCAN1_Init 1 */hfdcan1.Instance = FDCAN1;hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV2;hfdcan1.Init.

Hi,I will be using STM32H747XI with a MIPI or RGB-24bit display and design screens using touchGFX. My question is does it support OTA  via QSPI flash storage as the Arduino framework has support for the OTA does the Cube IDE support it or can I use Arduino framework for the MIPI or RGB-24bit displays?

  Hi I followed this yt-guide for CAN-bus https://www.youtube.com/watch?v=JfWlIY0zAIc&t=918s I'm however using a different type of nucleo board (L433RC-P in my case and F103C8tx in the video) and a different type of CAN-transceiver (MCP2561T-E/SN vs MCP2551 in the video). My board uses a different type of can periphery (can1 vs can). My solution to this difference was to just change all of the code where he writes can to can1. Yet checking with an oscilloscope, I don't seem to be sending any CAN signal. relevant code:

hi,i couldn't chase which location address allotted for OTP memory ?.As per data sheet of MCU - Stm32f401ccu6– 512 bytes of OTP memory allotted . Can anyone please detail me OTP location Start Address - End Address 

Hey guysIm using stm32h743 and nand flash connected with fmc.I searched to see how I can create my own external loader for nand(i couldnt find any for nand flash).I think i just need to adapt Loader_Src.c file to nand flash hal function and a linker to build the .stldr?Am I on a right way?

Apologies if I've missed something simple (and I probably have!), but I'm trying to convert ADC readings on the STM32F072 into actual millivolts and I cannot seem to put all the pieces together.Where I am currently stuck is the formula at the top of page 260 in the reference manual RM0091 Rev 10:VDDA = VDDA_Charac x VREFINT_CAL / VREFINT_DATAAccording to the note just under that formula, "VDDA_Charac is the value of VDDA voltage characterized at VREFINT during the manufacturing process. It is specified in the device datasheet."I've been all over the STM32F072xB (DS9826 Rev 6) datasheet and I cannot find any reference to such a thing as VDDA_Charac or the voltage at which the VREFINT_CAL is characterized at. Am I supposed to assume it is 3.3V? Is there some constant in the HAL that I should be referencing? I found a "VDD_VALUE" in stm32f0xx_hal_conf.h, but I don't think that's it.Thank you for any guidance you can provide. 

Hello, I am having an issue turning off trustzone on my device. While checking that the example project to blink the LEDs was properly working on my device (it wasn't, it kept getting secure faults.) I had gone into the STM32 Programmer to change some options to see if it would fix anything in regard to why I kept getting secure fault errors on my device. I accidentally locked WP1A and WP1B. Then I attempted to fix this by turning on and off the trusted level. Now I am stuck with WP1A and WP1B locked, trustzone enabled, and my RDP stuck at 55. I've tried this article with no avail: community st / s / article / how-to-disable-trustzone-on-stm32u5-seriesAnd I've even tried accessing it with BOOT0 set to VDD. Is my board bricked? Is there anything I can do to fix this? Any help is greatly appreciated. Additionally, is there any guide to make sure that GPIO_IOToggle_TrustZone is properly working and setup other than the Readme?

Hello. I have three question about using classical CAN frame with FDCAN controller.I am using STM32H743VIT6 MCU on my PCB. 1. If system clock(label in ioc file: SYSCLK) is too low, can it make impossible to use CANbus? 2. If I using only classical CAN frame, does Nominal bit timing parameter(Nominal Sync Jump Width, Nominal Prescaler, Nominal Time Seg1/2) only consider and Data bit timing parameter ignored? or both bit timing parameter use for CAN 2.0 communication?    2.1 I am using KVASER Bit Timing Calculator to set timing parameter. what is appropriate sample point value for STM32H743?    2.2 There is Tseg1, Tseg2, SJW at KVASER Bit Timing Calculator for CAN FD. Does Tseg1 = Time Seg1, Tseg2 = Time Seg2 and SJW = Sync Jump W

Hello,maybe someone has an idea or can share an similar experience. Since I'm currently in the evaluation phase for selecting an MCU for our new industrial embedded project. I want to inspect and analyze this problem, to be sure the used MCU is working fine and i can use it (STM32H735IGK6).Issue:Pushbuttons on different EXTI-Interrupt  randomly fires twice or more times. Some GPIOs are effected, but not all, i have tested.Setup:Own PCB-Layout, 6 Pushbuttons, every one is debounced with 10kOhm and 10nF. Signal looks fine on scope, no bouncing can be seen with scope, absolutely clean signal.Test 1:apply a 200mHz sine-wave directly to the button pin. Expected behavior is: one interrupt on rising one interrupt on falling signal (due to the 200mV hysteresis on every input pin, as mentioned in datasheet). Behavior in RealLife: as soon as the voltage level on the pin reaches the s

While replicating the method of integrating DSP libraries into my STM32 project as discussed in the following thread: tutorial , I encountered the error #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" during the project compilation. I'd like to share a solution that proved effective in resolving this issue. Upon inspecting the "arm_math.h" file, I observed that, after the preprocessor directives, there is an inclusion of the header file containing information related to the device's peripheral access layer, in my case, "stm32f407xx.h". The solution involved simply moving the `#include "stm32f407xx.h"` directive to the beginning of the "arm_math.h" file. Following this modification and performing a clean build of the

I want to use tim 2 at the frequency of APB1 and not to the sysclock how i can do that, can somoene explain me or look at my code at the bottom to help me i want to use the 0.09375 frequency for my projet. thanks 

I'm wondering what happens with the EDATA sectors when bank swapping is enabled.In the GetBank_EDATA() helper function in the FLASH_EDATA_EraseProgram example, the FLASH_OPTSR_SWAP_BANK flag is not checked, so it would seem the EDATA areas do not swap when the banks are swapped.Is that indeed the case?