STM32 MCUs Products

Target MCU: STM32L151ZETx (LQFP144)Main Clock Frequency: 32 MHz When the MCU is first powered on, it takes about 41 ms to reach the while(1) loop in the main() function, based on the code shown below. For my product requirements, I would like this startup time (from power-on to reaching while(1)) to be reduced to around 16 ms. Is there any way to achieve this reduction? Any suggestions or optimization techniques would be greatly appreciated. /* Includes ------------------------------------------------------------------*/ #include "main.h" #include "adc.h" #include "dma.h" #include "rtc.h" #include "tim.h" #include "usart.h" #include "gpio.h" /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); int main(void) { /* Reset of all peripherals, Initializes the Flash interface and the Sy

I tested the LSE CSS function on the Nucleo-L053, but I found that short-circuiting the crystal oscillator pins failed to trigger the CSS interrupt. The code configuration is as follows plz give a clue or the flow of LSECSSvoid SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; /** Configure the main internal regulator output voltage */ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /** Configure LSE Drive Capability */ HAL_PWR_EnableBkUpAccess(); __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.LSEState = RCC_LSE_ON; RCC_OscInitStruct.HSI

The Reference Manual for L4 series (RM0394) says on page 1007:"When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register mayreturn unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical.It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal."1. What does "asynchronous clock" mean?2. The block diagram, Figure 337 on page 988 shows a "Synchronization" block but is vague as to what this pertains to.3. Also, what is meant by "kernel clock"?  If I am using the LSI oscillator for the clock source (CLKMUX = 0), where does this "lptim_ker_ck" come from?  How is this mapped to LSI clock?  This is confusing.4. If the LPTIM1 is being fed

I'm experiencing FDCAN Memory Access Failures on the STM32H503KBUX during CAN Rx. I am also experiencing intermittent CAN Rx message drops (every 1 in a 200), and I believe the two are related since no others errors are firing. I know the drops are happening on the STM32 because I can see the messages on the bus with my CAN debugger and there are no error frames. I'm struggling to understand why this Memory access error is happening and how to proceed with solving it. The only info I can find is in rm0492. However, it doesnt really say what might cause these events to happen. Other relevant info:- Using internal clock

Hello,Is it possible that STM32f207ZGT6 purchased in 2025 from an official distributor have an old silicon revisionrev_id = 0x200f?

I am having a problem reading SPI data on an STM32F407 where it always returns 0x00. I actually have this working using HAL on the same hardware, however for legacy reasons I need to get this working with SPL. This application is just sending clock signals to the slave and reading the received data. There is no activity on MOSI.I can scope the signals and see the expected traffic on the SCK and MISO so I at least know my clock transmit is working. I just can grab the correct read data. Here is my code. I feel like I'm missing something basic for SPL. Any insight would be helpful.#include "main.h" #include "stm32f4xx_spi.h" #include "stm32f4xx_usart.h" #include "config.h" #include "board_init.h" #include "gpio.h" #define TIMEOUT_TIME 1000; uint16_t SPI_TransmitReceiveByte(uint16_t data); uint16_t spiData; void main() { uint32_t loopCounter = 0; SystemInit(); init_IO(); SPI3_Init(); powerOnLED(); while (1) {

According to some reference it is good to have ground polygon under IC 1. Is it okay to have ground polygon under IC? 2. Does it effects heating issue?3. I saw two hole behind the IC of nucleo 144 board. What that mean? 

On my current board the STM32G030 is getting very hot.  I have even tried a board with no connections to the processor and all pins set to analog.  I have checked the power supply and it's 3.3V.  The board runs OK but I am worried about the processor temp.  I have attached a schematic of the board.  Could something internally be configured to cause this heating?  

Hi all, I’m working on enabling USB High‑Speed (HS) communication on an STM32F446RE using an external USB3300 ULPI PHY, but I’m running into several issues and can’t get ULPI communication working. Current Issues: DIR pin stays high – it appears the STM32 never gains control of the bus. The ULPI clock runs at 60 MHz (derived from the USB3300’s 24 MHz oscillator), and while enumeration occurs, the USB middleware fails to initialize correctly, resulting in the device being detected as an “Unknown Device.” To enable PLLQ, I tried enabling the USB FS peripheral and then disabling it to avoid pin conflicts with the HS lines, but it didn’t help. Toggling the USB3300 reset pin had no effect. Configuration Details: Initial setup done via CubeMX. USB_OTG_HS configured for ULPI interface. RCC and PLL settings look correct, but PLLQ doesn’t remain enabled. Tried USB Device middleware

We are working with the STM32 Nucleo-G474RE board and using two quadrature encoders—NEMA 23 and NEMA 34—connected through AM26LS32 line receivers to TIM2 and TIM3 respectively, configured in encoder mode. In our project, we initialized TIM2 and TIM3 with `CounterMode_UP`, no prescaler, and appropriate encoder mode settings. We initially tested with pull-down resistors and counter mode set to down, but encountered erratic behavior: encoder counts would overshoot, then suddenly reset to 0 or toggle between 0 and 1. We then tried changing the GPIO configuration to pull-up with counter mode set to up, but received no response from the encoders. Despite using `HAL_TIM_Encoder_Start()` and observing the encoder signals on an oscilloscope (which looked clean), the counter readings remained unstable or stuck. We are using the ITM SWV output to log values via printf. We would appreciate any insights or suggestions from the STM32 community on solving this encoder reading issue, especially in

Hi team,            I am working on stm32F7 discovery board, I am working on USB MSC Device however i am not getting , how to configure external flash of this discovery board as Mass Storage. My main goal here is as soon as i connect the controller to PC, the external flash has to detect as mass storage device (predefined size).  regards,Shikamaru  

Hi all, I have a custom board and application using the mentioned MCU, when I use the "run" with the Release option  on STM32CubeIDE and once I use the board alone the FW starts flawless as soon I power up. Now when I use the STM32CumeProgrammer to upload the "Release" bin file the board do not start the FW after powering up the board but need to press reset for it to start. These behavior tells me is not an issues with the NRST's RC circuit. Could anyone help me to solve this issue, cause have a production waiting to solve this issue since all the boards were programmed using the  STM32CumeProgrammer for speed in production and now all of them need to use the reset button to start.Al OB are as suggested in the forums and documentation nBOOT_SEL=1, nBOOT0=1, nBOOT1=1 Thank you in advance.

Hello,I am working with an STM32G431K8T6and using the LL library to configure SPI in master mode.The issue is with the MISO pin (PB4).The pin is configured as SPI input, with no pull-up or pull-down.When PB4 is left unconnected, the voltage is measured at 3.3v.If I short PB4 directly to GND, the current goes up to about 65mA, which looks like the pin is driving strongly,similar to push-pull output.Because of this, the SPI slave cannot pull the line low enough, and communication fails.Configuration Details:void MX_SPI1_Init(void) { /* USER CODE BEGIN SPI1_Init 0 */ /* USER CODE END SPI1_Init 0 */ LL_SPI_InitTypeDef SPI_InitStruct = {0}; LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; /* Peripheral clock enable */ LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1); LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA

Hi, I have been trying to implement a logic to flash the updated firmware on top of existing with established DFU mode and using stm32cubeprogrammer. Where I chosen bin file for flashing and I provided the starting address as well. For confirming I have added enough debug prints and from that i never seen the erase function never being called when push the new update through USB.pls see the logsDFU Media registeredUSBD Started1.....6.....GetStatus Add=0x08020000 Cmd=0x016.....GetStatus Add=0x08019000 Cmd=0x016.....GetStatus Add=0x08019000 Cmd=0x01FLASH_If_Read addr=0x40022070 len=46.....GetStatus Add=0x40022070 Cmd=0x01FLASH_If_Read addr=0x40022070 len=46.....GetStatus Add=0x40022070 Cmd=0x01FLASH_If_Read addr=0x40022070 len=46.....GetStatus Add=0x40022070 Cmd=0x01FLASH_If_Read addr=0x40022070 len=46.....GetStatus Add=0x40022070 Cmd=0x016...

I'm using STM32F429I-DISCO with external SDRAM and DMA2D to render graphics.CPU run at 180 MhzSdram 90mhzLtdc clock: 3mhzLcd : 240*320 color RGB565Issue:I use DMA2D to fill the screen, then on Transfer Complete interrupt, I trigger a second DMA2D to draw a sprite.It works fine in debug mode, but in real-time, the sprite is not drawn.If I switch to polling mode (HAL_DMA2D_PollForTransfer()), it works correctly.The interrupt may fire before SDRAM is truly ready for the next transfer.The question:How to reliably chain DMA2D operations with SDRAM in interrupt mode to fully offload cpu?

Hi,I have a question regarding the backup SRAM in the STM32U5. The reference manual is not clear about this:On the one had, it mentions the following Which seems to indicate that it is possible to place the device in standby without powering SRAM2. HOWEVER, it also says this:

Hello,When using stop mode 3 with the stm32u5a9j chip, I noticed a unexpected behaviour when exiting stop mode 3.I have a device connected to the stm32 chip which wakes up the stm32 on rising edge on one of its pin ( GPIOA0 ). This interrupt can be triggered while the stm32u5 is in run mode or in stop mode 3. When the stm32u5 is in run mode and if this interrupt is triggered, only the the EXTI Line0 interrupt is generated by the NVIC as expected.But when the stm32u5 is in stop mode 3, sometimes the NVIC generates 2 interrupts when exiting stop mode 3  the EXTI Line0 interrupt and then the PWR wake-up from Stop 3 interrupt ( both with default priorities, respectively 19 and 85 ) and sometimes ( less often ) only the PWR wake-up from Stop 3 interrupt is generated. It's not clear why the EXTI is generating an interrupt and sometimes it does not when exiting stop mode 3. Is there a way to make sure the EXTI is also generating an inter

Hi, I'm using the STM32H753-NUCLEO Board for some SW development, and I'm having some issues with the SPI Handling.I'm attempting to transmit a single 16-bit data packet, however on the scope I'm transmitting two 16-bit data packets. When I change my data packet type to 8 bits, I'm transmitting 4 8-bit data packets.I've scoured the RM0433 manual but cannot find the register which tells the peripheral to only transmit a single data packet.Could someone point me to the correct register and what it should be set to to achieve this please?

HiI created a composite USB device with CDC and UVC classes using usbd. The device is detected, camera image streaming works, and data transfer via CDC (virtual serial port) also works. However, after a random time, communication on the CDC data out endpoint stops. Reopening this endpoint solves the problem. The same thing happens with EP0. When I repeatedly open and close the serial port, EP0 stops receiving data after some time. If I stop video streaming, CDC communication is stable.Sometimes I also get an incorrect video frame when data is transmitted via CDC. I'm using FreeRTOS, but running everything in a single thread didn't solve the problem. I have no further ideas what could be wrong.Any ideas?Artur

I am using two NUCLEO-U385RG-Q boards for I3C communication — one configured as the Controller (Master) and the other as the Target (Slave). I am trying to implement an IBI event with Pending Read Notification, and would like to know whether it is possible to perform Repeated START between the IBI and the subsequent Private Read? The transfer format for Pending Read Notification can be referenced in the following document, specifically Figure 6 – MCTP over I3C packet transfer format: I3C Target to I3C Controller:Management Component Transport Protocol (MCTP) I3C Transport Binding Specification  

Hi everyone! I have a working project based on STM32F746 with LCD, Ethernet and SDRAM(IS42S16160J-6TL) and now we are moving it to STM32H753II. I set up a FMC controller and tested whole SDRAM region with 8, 16, and 32 bit access. I use GCC. During this migration I discovered a line of the code that always generate a HardFault error with UNALIGNED flag set. This is this line: if (strncmp(data + i, boundary_str, 9) == 0) from: for (i = 0; i < len; i++) { if (strncmp(data + i, boundary_str, 9) == 0) { boundaryOffset = i + 9; break; } } data is placed in SDRAM like this: char eth_rx_buf[MAX_LENGH] __attribute__((section (".sdram_noncached"))); and boundary_str like this:

Hello everyone, I am working with an STM32H753ZI board and I want to set up CAN communication. I’m a bit confused about what changes I need to make. Here are my main questions: Does the STM32H753ZI use the regular CAN peripheral or the newer FDCAN peripheral? In CubeMX, which settings (baud rate, prescaler, seg1, seg2, etc.) are recommended for 500 kbps? Since the H753ZI board doesn’t have an onboard CAN transceiver, which external transceiver IC (e.g., MCP2551, SN65HVD230, TJA1050, etc.) would be best to use with it? Are there any example CubeIDE projects or reference codes specifically for CAN/FDCAN on the STM32H7 series? How to setup the pinout  configuration and clock configuration. I want to make sure I configure the peripheral and

  Hello, I am working with an NUCLEO-H753ZI (ADC1/ADC2 with DMA1/DMA2, and ADC3 with BDMA).My goal is to store ADC conversion results directly into a uint32_t buffer using DMA, so that the 16 valid bits from the ADC are automatically zero-extended to 32 bits in memory. The reference manual describes the possible data widths (byte, half-word, word) for peripheral and memory sides, but I could not find a clear statement about what happens when: Peripheral data alignment = half-word (16 bits) Memory data alignment = word (32 bits) Does the STM32H7 DMA (DMA1/DMA2 and BDMA) guarantee that the upper 16 bits are always zeroed when transferring 16-bit peri

Akkording to AN3155, July 2025: "The highest tested baud rate (BHigh) is 115200." Have tried with 921600 and that seems to work fine.  Is the recommodation from ST that not use above 115200?

HiI modified nBOOT_SEL Bit, but still the PA14-BOOT0 Pin level has no effect. The CPU starts always on in Main flash memory. I have these 2 situations (RM0490 Rev 5 page 53) If PA14 is low level: Main flash starts. This is okIf PA14 has high level: System memory (Internal Bootloader) should start. This is not working. Always application on flash memory starts.This is the Flash_OPTR content: