STM32 MCUs Products

I have a doubt about can a general purpose timer generate dead time like advanced timer without changing the duty and frequency is this is possible i tried with center aligned mode but it changes the duty is there is any possiblities??

Hello,I need counter which should wakeup system from stop2 mode at every sequential time.So currently use below setting and it works fine and wakeup at every ~4.16 minutes. But I want it should wakeup at max time of 30minutes (not fixed but looking for max time it can achieve). So thinking to use Repetition counter so that it can repeat the same counter and once repeat counter complete it will wakeup the system. But it's not affecting with repetition counter value. works same at zero.void MX_LPTIM1_Init(void) { LPTIM_OC_ConfigTypeDef sConfig1 = {0}; // 1. Enable LSI Clock RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } // 2. Select LSI as LPTIM1 clock source __HAL_RCC_LPTIM1_CONFIG(RCC_LPT

Hi, What is the frequency of timer2 which is of 32  bit with prescaler value 0 for NUCLEO-H755 board and how to check it ? 

Hi,Is there any way to debug an application launched from external flash memory? I use J-Link and IAR, the application is loaded into flash but I am not able to start debugging. I assume that in order for the microcontroller to even start executing code, XSPI must be configured first and memory mapping must be enabled. Should the debugger do this? Is it even possible?BRArtur

Given that my QSPI driver and external loader for the W25Q128JVSIQ are already working, is there a hidden CubeProgrammer/DFU-descriptor trick that lets the stock USB bootloader read/write my external QSPI flash at 0x90000000, or must I build a custom USB-DFU bootloader that:Initializes QSPI and advertises the 0x90000000 regionHandles read/write/erase transfersso I can flash firmware onto the external flash over USB? If I do go the custom route, can I still use CubeProgrammer for the update, or do I need to write my own host application?

HiiI am using stm32g0b0cet6, while writing bootloader, i am confused with the page number and the total storage.Its total storage is 512 kb, According to the reference manual, The Main memory is shown like belowQuestion1: If each page is 2kb & total number of pages are 383, then total flash should would be 2x383 = 768 kb. (contradiction ot total flash size)Question2: According to the memory address given of first & last page, the total memory comes up after calculation is 512 kb. here is the calculation:0x0807F800(last page starting address) - 0x08000000 (0th page starting address) = 0x7F800 = 522240 bytesAdd the last p

 Dear all; I have a *** question but it dont work can we have quantity 2 different i2c bus 1 is reconized but not the second bus  /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_LTDC_Init(); MX_QUADSPI_Init(); MX_FMC_Init(); MX_I2C2_Init(); MX_I2C4_Init(); MX_SPI1_Init(); MX_UART4_Init(); MX_USART1_UART_Init(); MX_TIM3_Init(); MX_DMA2D_Init(); /* USER CODE BEGIN 2 */ int P=10000; HAL_TIM_PWM_Start(&htim3,TIM_CHANNEL_4); //htim3.Instance->CCR1=50; __HAL_TIM_SET_COMPARE(&htim3,TIM_CHANNEL_4, P); HAL_StatusTypeDef result; uint8_t i; for (i=1; i<128; i++) { /* * the HAL wants a left aligned i2c address * &hi2c1 is the handle * (uint16_t)(i<<1) is the i2c address left aligned * retries 2 * timeout 2*/ //ret = HAL_I2C_IsDeviceReady(&hi2c2, (uint16_t)(i<<1), 3, 5); result = HAL_I2C_IsDevi

Hello,I’m using the STM32H503CBT6 microcontroller in my project. At this stage, the firmware simply toggles a single LED. I’m using STM32CubeMX (code configurator) and compiling with STM32CubeIDE. The system is configured to run at 250 MHz using a 16 MHz HSE with the PLL, according to the recommendations in the documentation.Hardware Configuration:NRST pin is pulled up to 3.3V with a 4.7k resistor and has a 100nF capacitor to GND.BOOT0 is pulled down to GND with a 10k resistor.Both VCAP pins have 2.2µF ceramic capacitors.All unused GPIOs are left in floating mode via CubeMX configuration.VDD is supplied with a stable 3.3V.Observed Issues:The system enters a fault state randomly, between 10 seconds and 10 minutes after power-up.In the fault state:VDD remains at 3.3V.NRST pin oscillates between ~0.5V and ~0.9V.VCAP voltage drops to around 1V (where it should normally be ~1.36V).Before ent

I'm working on a project which uses DMA to pull data from an external chip controlled by the FMC into a buffer in AXI SRAM, and am seeing a much lower throughput than expected. It looks like the FMC is idle for long periods of time, and I'm looking for some insight the cause of the downtime. Where are the delays being introduced? Are they inherent to the FMC peripheral, caused by its current settings, or a result of how it's being accessed? Also, which clock connects to the DMA controller on the H7 series, and could the DMA clock also be limiting performance? Additional details: The FMC is configured for asynchronous accesses to SRAM with an 8-bit data bus and a 12-bit address bus (full config is pasted below). The FMC is clocked at 200MHz, the core is clocked at 400MHz, and I'm not sure about the DMA controller clock since it doesn't show up in any clock diagrams I can find. I'm using development hardware (an old Nucleo-H743ZI2) and just monitoring

Hello,I implement RS-485 on STM32G491. I receive with ReceiveToIdle_DMA and I also transmit with DMA. I need to know if currently something is being received because that means I cannot send data now because RS485 is half-duplex. As far as I know I cannot use IDLE flag as it clears after interrupt and I need to know if RX line is now IDLE or now I am receiving data.In sumarry - what condition should I check before sending data and changing DE state of the transceiver to make sure RX is silent now.Looking forward to your replies!

Hello All, I am developing a design based on STM32N647A0 and have limitation on the number of pins to accommodate 16 data lines. The PSRAM used in STM32N6DK board is APS256XXN-OBR-BG and is based on 16 data lines. So, can i use APS6408L-3OBM-BA, PSRAM that has 8 data lines because of the limitation of number of pins. This will help me to stay with the STM32N647A0 part number? Please suggest on this.  Also, I understand the data rate may be compromised by using APS6408L-3OBM-BA, but I want your suggestion, if the STM32N647A0 device will be compatible to work with 8 data lines PSRAM. Please share your valuable suggestions on the concerned issue. Best Regards, Sakshi       

Hi all, Is there a Modbus tcp/ip Server (Slave) and client (Master) examples for STM32 Nucleo F429ZI board or any other similar boards?  Thanks,

Recently I have encountered a strange issue I cannot really explain...I have a firmware that manages serial UART communication with a callback that has a state machine with 3 states.In the first state, UART is set to perpetually expect 1 byte of data until a specific value is received. If the value is received, another byte is set to be read via UART_Receive_IT and SM proceeds to the next state.In the second state, the received byte is considered message length and UART_Receive_IT is set to read the expected amount of bytes.The third state is supposed to happen when the expected amount of bytes is received and all parsing is done... however, it is never triggered when the serial data is longer than 49 bytes.I am sending data with RealTerm. Short messages work just fine, but then I need to send 147 bytes. In the debug, I can see from the state of huart2 handler that RxXferCount starts at 147 and decrements until 98. Then, UART_RxISR_8BIT i

Hello,Trying to achieve wakeup system at every 60 sec or more using LPTIMER1 in STOP2 mode.Observation:1. STOP2 = enable and LPTIMER = 60 sec --> Wakeup not work2. STOP2 = disable and LPTIMER = 60 sec --> Wakeup work3. STOP2 = enable and LPTIMER = 2 sec --> Wakeup work4. STOP2 = disable and LPTIMER = 2 sec --> Wakeup work void enterLowPowerMode() { HAL_UARTEx_EnableStopMode(&hlpuart1); HAL_SuspendTick(); HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI); HAL_ResumeTick(); Reset_SystemClock(); HAL_UARTEx_DisableStopMode(&hlpuart1); }Using LPTIMER1, below is the configuration, static void MX_LPTIM1_Init(void) { /* USER CODE BEGIN LPTIM1_Init 0 */ /* USER CODE END LPTIM1_Init 0 */ LPTIM_OC_ConfigTypeDef sConfig1 = {0}; /* USER CODE BEGIN LPTIM1_Init 1 */ /*

can anybody answer please, if i costmised board based on  bg431besc1 board  it needed to upload boot loader file in stm32g431 controller to run in stm32ide code ?

I am using IAR + STLINK-V3PWR for my project. If I stop and resume program execution, on the STM32L433 MCU the TRACE_IOEN bit is activated and SWO intercepts pin PB3 . How to disable SWO ?

We are currently using the STM32H723VGT6 MCU (1MB Flash) in our application.We would like to clarify whether this MCU supports execute-in-place (XIP) from Quad-SPI flash or if Octal-SPI is required for XIP functionality.In the future, if our application requires 2MB of internal flash, we plan to upgrade to the STM32H743VGT6, which is pin-to-pin compatible and also supports Quad-SPI.As we are designing a common schematic for both MCUs, we would like to confirm:Is a single Quad-SPI interface sufficient for enabling XIP on the STM32H723VGT6, or does it require an Octal-SPI interface for that purpose? 

I want to use port PA9 of STM32H743XGH6 as “FS_VBUS”. In this case, which number should I put in the target register for the alternate function? I understand that if I use CubeMX, it will set it automatically.

Hi,I want to configure my device as a USB Microphone. However the cubemx generates code for USB speaker and the device is detected as STM32 Audio Class Speaker. Can anybody suggest a solution or Cube Example for USB Audio class with Microphone  codes/drivers. My devices are STM32H743, STM32H745, STM32H750, STM32H753, STM32H7A. I am using an analog microphone which is connected to ADC via preamp. Thank you

Hello,I found some discrepancy in BOR configuration for STM32U083CCT6 processor between reference manual [1] and HAL implementation [2]. It concerns BOR_LEV[0:2] bits (bits 10:8) in FLASH_OPTR register. The RM [1] talks of four levels (000: 1.7 V, 001: 2.0 V, 010: 2.2 V, 011: 2.5 V, 100: 2.8 V), in HAL [2] bit 8 is used to enable BOR (OB_BOR_ENABLE in stm32u0xx_hal_flash.h, FLASH_OPTR_BOR_EN in stm32u083xx.h), and the next bits (the remaining two) are used to set the level, importantly, the RISING one (00: 2.1 V, 01: 2.3 V, 10: 2.6 V, 11: 2.9 V), and the next two bits (12:11, which are described in the RM as reserved) are used to set the reaction of the BOR circuit to the falling voltage (00: 2.0 V, 01: 2.2 V, 10: 2.5 V, 11: 2.8 V). So the implementation in HAL is wider (based on 5 bits) and seems more advanced than the one given in the RM. I will add that the erratum [3] is silent on this topic.So, the question is which BOR settings in the STM32U083 processor are corre

I'd like to use the DTCM ram in my code; how can I do ? Thank you

Hi,1.As it is mentioned in CM4 user guide and also explained in tutorial, 0th bit of PC is directly loaded to T bit.And CM4 supports only thumb state ISA.To execute/decode instructions in Thumb state 0th bit of PC should be 1 which means PC should always hold address with odd numbers (i.e ODD Locations).2.But in the attached screenshot,Top left corner - core register window,top right side has disassembly window,Bottom Left-expressions window3.Actual queries are:3.1 why PC is holding even address(PC:0x8000654 ). And in disassembly window, address of location from where instruction needs to be executed is also even and it is matching with value in PC which is correct(Current location :0x8000654).3.2 Once control jumps into generate_interrupt() function[Defined at locat

When a CAN message is not ACKed by other nodes, if auto re-transmission is set, bxCAN will re-transmit the message infinitely. This floods the CAN bus, especially if the message is of high priority.My solution is to enable the error passive interrupt (EPVIE), when EPVF is set, in HAL_CAN_ErrorCallback check which TX mail box has transmission error, and explicitly request abort, as follows:  if (hcan->ErrorCode & HAL_CAN_ERROR_EPV) { uint32_t tsrflags = READ_REG(hcan->Instance->TSR); hcan->ErrorCode &= ~HAL_CAN_ERROR_EPV; if ((tsrflags & CAN_TSR_TERR0) && !(tsrflags & CAN_TSR_TME0)) { SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); } if ((tsrflags & CAN_TSR_TERR1) && !(tsrflags & CAN_TSR_TME1)) { SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); } if ((tsrflags & CAN_TSR_TERR2) && !(tsrflags & CAN_

Hi, I am trying to send classical CAN messages using FDCAN with STM32h723vgT6 - based board. I am however having difficulties sending any packets (and receiving). Hardware setup:- DM-MC02 board, based on STM32h723vg (https://gitee.com/kit-miao/dm-mc02)- SIT1042 CAN controller, directly built-in the board. Thus, the respective CAN_H and CAN_L are directly accessible through the board's pin- (Device) ZDT_Emm_V5.0 stepmotor controller. Anyway it is just the device I am trying to send data to (https://blog.csdn.net/zhangdatou666/article/details/132644047)- CANable 2.0 - inspired USB device. What I am trying to do:I want to be able to send and receive cla

I am not sure I properly understand the STM32H7A3xI/G ADC frequency limitationIn the DEV13195 - Rev8 - Datasheet, section 6.3.21 16-bit ADC characteristics, table 93 ADC characteristics, page 143It says the fADC max frequency is 50 MHz with boost mode activatedThis specification seems to match the one ine the section 6.3.1 General operating conditions, Table 23. Maximum allowed clock frequencies, page 84where it also says that fadc_ker_ck maximum value is 50 MhzAnd the same clock fadc_ker_ck is describe at the final adc clock in the