STM32 MCUs Products

Does the system memory bootloader for the STM32L4P5xx consider RAM3 as valid SRAM for the stack pointer?After programming bank 2, and then setting BFB2, The device will not boot into bank 2.  The linker has the top of the stack at RAM3.  The value written to both 0x8000000 (bank 1) and 0x8040000 (bank 2) is 0x20050000.  I want to make sure this is correct.  By the way, this is the 512K part STM32L4P5xE.  The other relevant options bytes are set as follows: nBOOT1=1, nSWBOOT0=0, nBOOT0=1 (BOOT0=0).  When I clear BFB2 I can boot.  I have compared the flash memory from 0x08000000-Length with 0x8040000-Length, and they both match.

Hello ST Community,I’m working on a project using the STM32F205RBT7 and planning to integrate the Independent Watchdog (IWDG) for system recovery. However, I’ve encountered significant timing inconsistencies across multiple boards (tested on at least 4 custom and EVK boards). For example, when configuring a 125 ms timeout, the watchdog sometimes triggers as early as 120 ms and other times as late as 140 ms.This variability in the IWDG timeout raises concerns for time-critical applications. Has anyone else observed such behavior with the IWDG on this MCU?I’d appreciate any suggestions for improving timing reliability, or if switching to WWDG or a software-based watchdog might be better. My only hesitation with WWDG/software watchdog is their dependency on SYSCLK, which may not be fail-safe in certain failure conditions.Thanks in advance for your insights and recommendations.

I am trying to write to the flash memory of the STM32L4S5QIIX microcontroller on the EVAL-ADIN1110EBZ development board. I have also tried similar code on an STM32L4S5VITX microcontroller on a custom circuit board.Short example code:uint32_t flash_memory_address = 0x08100000; uint64_t flash_write_data = 0x12345678; uint8_t flash_read_data[4]= {0}; HAL_FLASH_Unlock(); FLASH_PageErase(0, FLASH_BANK_2); HAL_FLASH_Lock(); HAL_FLASH_Unlock(); __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); HAL_StatusTypeDef status = HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, flash_memory_address, flash_write_data); HAL_FLASH_Lock(); The full code and project files can be found at: https://github.com/landas/stm32l4s5-flas

Hi,I would like to configure the I2C frequency based on the input clock frequency. Is there a specific formula to calculate the I2C timing values? Also, I would like to know whether this formula is applicable to all STM32 microcontrollers, or if it varies depending on the MCU series.Could you please provide clarification on this, along with example code for configuring the I2C frequency using the appropriate register settings and formulas?Thanks,Sainath 

Hello,i have configured a timer interrupt an it seems like that interrupt preempt another adc interrupt. I configured the timer interrupt like that: NVIC_SetPriority(TIM1_BRK_IRQn, 2U); NVIC_SetPriority(TIM1_UP_IRQn, 2U); and the adc interrupt like that: NVIC_SetPriority(ADC1_2_IRQn, 1U); So my expectation would be that no preemption occurs from timer interrupt because priority is 2 (priority lower then ADC interrupt priority). To check if the interrupt priority of timer interrupt is the root cause of preemp

Anyone who knows that Development kit for below given part number(Connect D[7:0], PCLK, HSYNC, and VSYNC), and Can we video streaming via USB?STM32F407VET6.  

I have an STM32L011 on a board I am developing.I can enter the bootloader no problem, as per AN2606/AN3155.  I am using USART2, 57600 baud.I can program FLASH/erase FLASH/read FLASH - all works as expected.I note that the bootloader reserves 2048bytes of SRAM, I assume it's the addresses 0x2000_0000 .. 0x2000_07FF.When I try to use the memory read command to read from anywhere in SRAM (whether the bootloader reserved area or any other address) I get a NACK just after the address+xor-check-byte.I believe the protocol is correctly implemented because the same thing works reading from FLASH addresses (e.g. 0x0800_0000).Is there a known issue here (I have seen other posts on this forum with similar problems on other STM32 parts - but these are either unresolved or they are trying to read from the reserved SRAM which is expected to be NACK'd). 

I am working with a dual core STM32H755 and attempting to create a shared memory location for the two cores to access. I am attempting to do this by modifying the linker script.  I have added the following lines to the M7 core linker script, in the SECTIONS block:/* Shared Memory section for inter core comms */ .sharedRAMsection 0x30040000 : { .= ALIGN(4); KEEP(*(.sharedRAMsection)) . = ALIGN(4); } > RAM_D2 Then in one of my .c files, I have declared the following global variable:RegisterMap_t __attribute__((section(".sharedRAMsection"))) g_RegisterMap; However, when I debug I can see the address of this variable has been assigned to memory location 0x24000064, as seen in the watch window:

用SPI+DMA驱动AD4001，用片选信号代替 CONV，采集一个正弦信号。Normalnormal正常，循环模式却不对，求大佬解答！！Normal模式下，每次在 HAL_SPI_RxCpltCallback 函数里面重新启动数据正常，能看到正弦变化规律                                 循环模式下数据就不对了，采集的同样一个交流信号，我在半传输完成回调里面查看，按道理后半部分的数据应该是正常的正弦变化才对，实际却不是，但是去采集直流时又是正常的。                PS：缓冲区开的1200，感觉应该不会更新这么快，就算更新应该局部的数据具有正弦规律    我得猜想：是不是因为我再keil里面是打断点查看的数据，并不会停下SPI+DMA 在循环模式下的硬件工作，导致后台一直在更新，keil显示的数据其实不对配置：配置的区别只修改了DMA是正常还是循环void MX_SPI1_Init（void）{/* 用户代码开始 SPI

Hello Tesla I need to run M4 from 0x08000000  and then M7 from 0x08100000. Is there any example ?   Exactly I v'done my BOOT that runs on M4 (0x08000000) loads the Flash , then jumps into M4 (0x08040000). Now i have to run M7 from 0x08100000, but i don't know how... Please help :)

Hi all.I'm new to STM, but have been designing and making embedded MCU products for over ten years.I was drawn to the STM32F105 series because of the USB DFU, to allow for field updates for prospective customers to update a product we're developing. Outside of USB DFU functionality, we just need 3x UART's, one GPI, one GPO. That's it. We steer clear of USART1 because of it's overlap with OTG_FS pins. We have got our product working using a ST-Link programmer, but not as yet using the USB DFU.Our USB connection just isn't enumerating. The wiring is correct when compared to off-the-shelf STM32 enabled boards with OTG USB interfaces.I am across the date code bootloader issue as described in AN2606, our chips definitely come with bootloader 2.2. I have VBUS from the USB-C tied to PA9 (OTG_FS_VBUS). Yes, USB-C but with the 5.1K resistors between CC1, CC2 and GND. NRST is pulled to 3V3 with a 10K pull-up. Boot0 and Boot1 is pulled to GND via a 10K pull-down, Bo

/** * @brief DMA Linked-list yWaveQ configuration * @PAram None * @retval None */ HAL_StatusTypeDef MX_yWaveQ_Config(void) { HAL_StatusTypeDef ret = HAL_OK; /* DMA node configuration declaration */ DMA_NodeConfTypeDef pNodeConfig; /* Set node configuration ################################################*/ pNodeConfig.NodeType = DMA_GPDMA_LINEAR_NODE; pNodeConfig.Init.Request = GPDMA1_REQUEST_SPI3_TX; pNodeConfig.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST; pNodeConfig.Init.Direction = DMA_MEMORY_TO_PERIPH; pNodeConfig.Init.SrcInc = DMA_SINC_INCREMENTED; pNodeConfig.Init.DestInc = DMA_DINC_FIXED; pNodeConfig.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE; pNodeConfig.Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE; pNodeConfig.Init.SrcBurstLength = 2; pNodeConfig.Init.DestBurstLength = 1; pNodeConfig.Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0|D

I am trying to implement a GPDMA driver in a C project that does not use HAL, and have been really struggling to get something working. I have read everything I can find on this peripheral, multiple times, and still don't quite understand how one would configure the registers without using HAL. The goal is to get circular DMA transfers from peripheral to memory (e.g. ADC to memory). The H5 reference manual gives this figure, which conceptually makes sense to me but I can't figure out the implementation.It seems like it should be relatively simple to setup in C with direct register access instead of HAL configuration structures, but I ha

I am trying to debug some functions to write to the memory mapped QSPI. When I go to debug it, I notice that before any functions even run the QPSI is in HAL_QSPI_STATE_ERROR, therefore I cannot test my code to see if is running because it is dependent on the State of the QSPI. My QSPI is a WinBond25Q128JVSQ. Is there a way to trouble shoot this?

Are the steps followed for RTC calibration the same for crystal and temperature variation?How is the calibration register value selected for temperature variation?

I have selected the RTC calibration as 512Hz. Will I be able to perform RTC smooth calibration if my frequency obtained on the RTC calib pin is beyond the range 511.75Hz - 512.25Hz. How do I calibrate the RTC beyond this range ??  

When trying to program the STM32L4P5RE, I get an assertion failure when trying to program the second bank like this:HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, data)This call fails if my address is in the second bank `0x08080000`.  Looking at the source code, I get an assertion failure here: static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data){ /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); <---- HEREI understand when DBANK (Or DB1M) is set, we cannot read the other bank.  So how are we supposed to actually program it?

Hello, I am working with an STM32G4 microcontroller and noticed an unexpected behavior regarding Bit 20 (BFB2) in the User & Read Protection Option Bytes.According to the reference manual, BFB2 is a read-only bit.After performing an option bytes erase in Keil, I expected BFB2 to be cleared to 0 (default).However, after a system reset, I observed that BFB2 is set to 1.I would like to understand:Who sets BFB2 to 1 after an option bytes erase?Is this controlled by bootloader behavior, internal flash controller logic, or some default hardware mechanism?

I have two Nucleo boards that are connected with a CAN bus (Transceiver SN65HVD230). I would like to communicate with standard CAN, eight data bytes, data rate 50000 bit/s. For the F407 all TX & RX events are triggering (reused old working code) the CubeMX settings (HCLK 168 MHz, periphiral clk 42 MHz) are: The G431 is not working as expected, the CubeMX settings (HCLK 170 MHz, peripheral clocks 170 MHz) are:

I'm trying to understand how the CSR register works. I though initially that the various reset reason bits are mutually exclusive. That turns out not to be the case. For example, I'm seeing SFTRSTF and PINRSTF together, and also BORRSTF with PINRSTF. I'm curious to know the possible combinations and what they mean.Looking at the reference manual, it looks like the bits *are* mutually exclusive, with exception of PINRSTF. This is presumably set because the other signals are ORed together and used to create a pulse on NRST. Is this reading of the manual correct?There is no PORRSTF in the CSR register. My guess is that a POR is signalled by having PINRSTF alone set. Is this correct?On a not unrelated topic, what is the minimum Vdd at which the flash can safely be written? I'm seeing ECC faults and flash corruption, which seem to be due to writing a flash log entry when the battery is almost exhausted. I want to mitigate against this by detecting BOR or another

Hi,I am using nucleo-l476RG board.I am new to USB audio, I am trying to create USB Audio class (Speaker/MIC) using HAL. I am sucessfully able to create a node for speaker and MIC in my laptop. But unable to send and receive the data over USB. Can anyone suggest me any example or any documentation which can help me to achieve my goal.Thanks 

I have WeAct studio's STM32h750VBT6 board. i am trying to access Sandisk's 64 GB MicroSD card (formatted as FAT32) through MicroSD card Adapter using SPI1. I am not able to access memory card. i have enable SPI1 and made enable PB1 (SD_CS) as gpio_output and made it high. Also cross checked the hardware connection too, they are properly connected. i have provided 5v to Micro SD card adapter. still it issue persist. while debugging, i observerd fres is showing FR_NOT_READY. i am not able to figure out what's the issue. i have tried pull up on all pins as well  as pulldown but still the same. tried different prescaler too but same. i have use Tutorial-STM32CubeIDE-SD-card for reference.fres = f_mount(&FatFs, "", 1); if (fres != FR_OK) { printf("f_mount e

I made a custom board using a C091KCT6. I assumed I would be able to figure out a way to display data in real time using printf. Unfortunately, I did not make provision to expose PA2 and PA3 (or indeed any pins other than the ones used by my board). PA2 is in any case in use as SPI1 MOSI. So I have pretty much accepted that I need to make a new custom board, and I am keen to ensure that I will be able to use printf this time!I believe that two good solutions are to buy the STLINKV3-SET and either a) re-design the board to expose the PA2 / PA3 UART to that ST-LINK or b) re-design the board with an MCU that has a SWO pin and expose that to the STLINK-V3.I would like two kinds of help, please: if I do not need to buy a new debugger or re-design the board, it would be great to hear how I can use printf with the setup I have,

(Please see attached PDF for best formatting and screenshot images. Complete code of main.c and usbd_cdc_if.c are also attached as txt.)Hi everyone, This is my first post! Please excuse any mistakes I might make in my question :).Question & Problem Description:I am trying to use the USB_OTG_HS functionality in Full Speed (FS) Mode on a custom STM32H723ZGT6 microcontroller custom PCB. However, the USB is not detected by any computer — nothing appears when I plug it in (no device, no "unknown/unrecognized USB" error, no activity at all).I am using ST-Link/V2 for programming/debugging. The Project so Far:Successes of my Project:I can get the LED in PA10 to blink with programmed interval (using a specific HAL_Delay() time), turn ON o

Hallo, the information written on rtcbackup register, is retained when micro is powered off?Or the information will be lost?