STM32 MCUs Security

Hi,In TFM and SBSFU applications, by default the anti-tamper protection is enabled for both internal tamper events and external tamper events. It is activated at the start of TFM_SBSFU_Boot, and remains active. In case of tamper detection, sensitive data in SRAM2, caches and cryptographic peripherals are immediately erased, and the tamper interruption triggers a reset and the application is blocked (can't boot).I'm using the anti-tamper protection in TFM with stm32U585, but I don't want the tamper interruption to trigger a reset, I have changed the default configuration in TAMP_IRQHandler(), but still a reset is triggered and the application is blocked at tamper detection, I have tried to catch reset causes (reset flags), and I have found a software reset flag (Set by hardware when a software reset occurs.) and NRST Pin reset flag (Set by hardware when a reset from the NRST pin occurs.), So I wonder what would be the cause of NRST reset, and is there any relation between NRST , TAMP an

What are the STM32 MCUs, support KMS middleware feature ??is STM32H753VI supported this KMS feature ??If NO, is there any way STM32H7 can generate Pair of Keys on the fly during run time to create Self Device Certificate ??

..

@JHOUD​ @TDK​ @Dimitrios Bako​ I have configured HDP as follows :By Bootloader .icf details are :define symbol __ICFEDIT_region_ROM_start__       = 0x0C000800;define symbol __ICFEDIT_region_ROM_end__        = 0x0C007FFF; Configurations when i debug the code are also fine :Now from Bootloader i Jump to my secure application in which i Enable Hide protection :HAL_FLASHEx_EnableSecHideProtection(FLASH_BANK_1);issue is after this i am not able to jump to my nonsecure application. .icf details are:define symbol __ICFEDIT_intvec_start__ = 0x08020000;/*-Memory Regions-*/define symbol __ICFEDIT_region_ROM_start__   = 0x08020800;define symbol __ICFEDIT_region_ROM_end__    = 0x08027FFF;without enabling Hide protection it works fine.Am i missing something?

Follow up of my previous messages on AES-GCM on STM32H753.I think that the ref manual is wrong: I implemented my code this way and the busy bit never clears.The HAL code is not polling on this bit neither.i've checked on other STM32 ref manuals it is the same description.Could someone from ST confirm this is a documentation bug or a misunderstanding from my side ?

Hi,I am using the the SecureBoot on a STM32L4 with the KMS, I have some questions related to the protections:As I use the KMS, I read in the UM2262: "With KMS middleware integration, SBSFU keys are no more stored in a section under PCROP protection but inside the KMS code running in the secure enclave". So what is the effect of activating the SFU_PCROP_PROTECT_ENABLE in app_sfu.h ?If I don't activate SFU_FWALL_PROTECT_ENABLE, can a malicious user application read the keys from the KMS code running in the secure enclave? If yes, does activating the firewall protection make the secrets from the KMS code running in the secure enclave un-readable by the User App ?I read in UM2262 that using RDP L1 is not recommended because WRP can be reprogrammed. So if I understood correctly, a malicious attacker with physical access to the hardware could disable WRP and use a malicious User App to overwrite the keys in the flash. However how could that malicious app be installed as it won't be signed wi

Hi I want to ask that In SBSFU example for STM32G474 in user app application Firmware update is done using ymodem protocol i.e. UART can we used SPI protocol instead of this is this possible to use SPI or there is any limitation????? Please suggest

Do we have provision to configure STM32H753 as Secure Mode or not using SECURITY Pin in Boot selection ??or is this completely owned by STM ??is Devices received with enabling SECURE MODE it self ?? as mentioned in below Diagram ?? is STM does this SECURITY Bit Enabled in manufacturing itself ??

Hi,One of the requirement for the FLASH layout on dual bank product (like the STM32L4 that I use) is that the FWALL code section overlaps the the FWALL NVdata (see the attached image). If I understand correctly the reason is that if the banks are swapped the keys stored in the Secure Engine Code are still protected by the Firewall. My questions are:Can the banks be swapped without performing a mass erase first ? If not than what is the advantage of that overlap rule.How can the banks be swapped? (I know from the attached image that if SYSCFG_MEMRMP / FB_MODE = 1, banks are swapped but how can those variables be set practically ?) If the KMS is used, the keys are stored in the FWALL NVdata Code section not in the FWALL Code section. If the FWALL NVdata section is bigger than the FWALL Code section and the banks are swapped, isn't that possible the keys are outside the firewall protection ?Thanks in advance, Benjamin

Hello everyone I am working on 1 image example for STM32G474 I want to ask that what we can achieve using this.....We are able to download new firmware image or Not ?????????

@Jocelyn RICARD​  We need secure storage to keep Private Keys and certificates for TLS communication on STM32H753.To achieve this we found STSAFE-A110, but interfacing and to bring in this peripheral, it is time taking in terms of re-spin PCB design etc.Instead of this, can we choose PCROP protection mechanism, like converting Data to Instructions with help of scripts and then store them under PCROP protections ??is this solution looks feasible ??

One of the variable in my program is the program version ie 200 for version 2.00. I log it to my debug log and I display it for the customer. The program version must also be passed to the SBSFU post build script. Is there any way to do this so the SBSFU version stays synced with my program variable?

I'm using for the first time the RNG of STM32H753. I have a "clock error" which means that rng_clk is too slow compared to HCLK.The reference manual mentions the following: Is it a problem to just disable the clock error detection since it seems that the level of entropy fits the statistical benchmark ?Right now I disabled the clock error detection, kept rng_clk to the default value(hsi8_ck) and the bit DRDY is never set after I enable the RNG.

My read protection is on and i can't turn it off by any tool.Hope i can get some help

Following this question, I am also confused about how to fill the key in the CRYP peripheral. I don't find the Ref Manual very clear The register description mentions the key as an array K and an array b where MSB of K are in lowest address register.But it seems to be different in the key registers section of the doc.Basically an AES key would be an array of bytes, and I can't figure out how I fill these bytes in the key registers... 

As per information, PCROP configuration has to be cleared on regression of RDP Level from 1 to 0. But on NUCLE-H753ZI evaluation board, PCROP configuration is not clearing on regression.But it is showing as OPTION BYTES Programming successful.Can you please help with this, as we locked on this and not able to program application on to this FLASH protected AREA.@Jocelyn RICARD​  Can you help with this ??

For sbsfu in the following parts:In AN5056 rev6, see section 8.5 How to validate a firmware image.In UM2262 rev8, Appendix JIt says: At the first user application start-up, if the execution is correct (for example after self-tests execution) the user application must call a running service SE_APP_Validate(slot_id) if available or update dedicated flags in RAM otherwise to validate the firmware image.What dedicated flags are those? How can I know about the slot_id?

I am working on STM32 crypto library and using STM32L433RC controller,I am facing the issue of signature mismatching.i have followed below stepsStep -1 Key generation using openssl tool for ECC256 curveopenssl ecparam -name prime256v1 -genkey -noout -out private-key.pemopenssl ec -in private-key.pem -pubout -out public-key.pemread EC keywriting EC keyopenssl ec -in private-key.pem -text -nooutread EC keyPrivate-Key: (256 bit)priv:  cd:3d:64:7d:dd:33:d1:d3:db:91:f5:99:be:0e:b8:  6b:16:8e:b2:20:b7:1d:c8:16:db:81:d0:57:07:4e:  04:58pub:  04:5a:bc:6d:ab:e3:38:64:25:86:79:2a:17:d8:8d:  09:ce:43:36:f6:a1:ba:2d:db:25:d6:6d:42:f6:7e:  a0:ea:3f:ba:85:fd:a4:10:08:15:ee:06:0e:d9:e4:  e7:44:50:82:4a:87:ea:46:74:8d:3e:33:a3:55:53:  6f:32:60:80:81ASN1 OID: prime256v1NIST CURVE: P-256Step -2Hash computation, sign and verify message file using openssl toolResult is verify okStep -3Importing private and public keys in STM32

HI I am looking for a link to download the older version of CryptoLib v3, I can only find links to download the latest CryptoLib v4 here which is not the version that I'm looking for. Thanks! https://www.st.com/content/my_st_com/en/products/embedded-software/mcu-mpu-embedded-software/stm32-embedded-software/stm32cube-expansion-packages/x-cube-cryptolib.license=1643055766390.product=X-CUBE-CRYPTOLIB.version=4.0.1.html

I have attempted the following:-Build and tested a simple app, called TestApp with STM32CubeIDE/CubeMX, runs fine on itself (without SBSFU)-Build and tested the SBSFU 2_images example, works fine.-The TestApp runs on the same hardware as the SBSFU example and I want to replace the example SBSFU UserApp with the TestApp.-To achieve this I copied all project settings from UserApp to TestApp.-Modified postbuild.sh call to use the TestApp.bin instead-Managed to build the SBSFU_TestApp.bin without errors-Flashed SBSFU_TestApp.bin according to the SBSFU UserApp instructions-SBSFU boots correctly and signals that the TestApp is started, but the TestApp does not run.I suspect the problem lies in the STM32L475VGTx_FLASH.ld file. These differ quite a bit in the UserApp and in the TestApp. In the TestApp, CubeMX has generated it. I tried to replace that file in the TestApp with the one from UserApp, but then the TestApp also does not run anymore, even on itself, without SBSFU. What complicates th

We are looking for FIPS 140-2 / 140-3 certified Secure Boot loader implemented with help of X-CUBE-CRYPT LIB for STM32H753VI MCU.if i see NIST-CAVP certification, it is mentioned as STM32L4 series, then is thios same certificate is applicable for STM32H7 ?? if not is STM will help us to get FIPS certification for STM32H7 series as well ..??Please share the details as much as possible on this.@Jocelyn RICARD​  can you help with this FIPS or can you redirect to someone who handles FIPS certification.

I found an application note for regression of RDP level using OEM keys via STM cube CLI .But my use case is to do it by firmware .Can it be done ?/Jaroslav HOUDEK​  @zqizh.1​ 

WIth oocd I try to do following steps:1) Send reset and halt command2) disable bit DHCSR.C_MASKINTS3) Enable interrupts into ISER reg4) Make any interrupt pending in ISPR reg5) Perform Step commandif readout protection is diasabled, core interrupt occurs, I can see that pending bit is reset.if readout protection set to 1, pending bit still set even if I will send Resume command for few seconds. So, if there are any connection between RDP and interrupts mechanics, where can I read about it?

..

You can found below a extract of my linker script:MEMORY { D1_CODE_RAM (xrx) : ORIGIN = 0x24070000, LENGTH = 64K FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K NVRAM (rx) : ORIGIN = 0x8020000, LENGTH = 64K }   .ram_code_load () : { . = ALIGN(4); _sdata = .; /* create a global symbol at data start */ *(.ram_code_load) *(.ram_code_load*) *RestApiServer.o (.text .text*) *Cryptographic_CM7.a:*(.text .text*) KEEP(*(.ram_code_load)) . = ALIGN(4); _edata = .; /* define a global symbol at data end */ } >D1_CODE_RAM AT> NVRAMWhat I expect is to found into my .map file the Cryptographic_CM7 .text code placed at 0x8020000 as it's done with RestApiServer.o code.What I get is the Cryptographic_CM7 library .text code placed at 0x8000000...Until now I had follow this PDF as ressources whitout any sucess. https://www.st.com/resource/en/application_note/an4296-use-stm32f3stm32g4-ccm-sram-with-iar-embedded-workbench-keil-mdkarm-stmicroelectronics-stm32cubeide-and-other-gnubased-