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Hello,is it possible to cascade multible STPM33 Chips? That means SPTM33 + Crystal as master -> two STPM33 CLKIN-> Last CLKOUT -> two STPM33 CLKIN 

Hi,I'm currently trying to run an image classification AI on a STM32H747I-DISCO board with the B-CAMS-OMV camera module bundle, using my own dataset. I was told it's good practice to use the same sensor for dataset collection and the final application, so I want to collect the images for the dataset with the B-CAM-OMV camera module aswell.I've seen that the model zoo provides many applications for the DISCO, unfortunately no simple USB-Webcam. I found such an application in the deprecated FP-AI-VISION1 pack, but it seems that my DISCO is a newer model and has another LCD (MB1166-A09), which doesn't work with the FP-AI-VISION1 pack.Does anyone know of a similar up-to-date application for simple taking images or has a different solution?

Hello,I am using STM32H750ZB variant for an HMI custom project and I am using SDRAM via FMC.When I configure FMC in cubeide1.19.0, I can't see the FMC_NBL0 and FMC_NBL1.I can actually add these pins as GPIOs, but I can't define the AF as AF12_FMC.I know from the datasheet that this package supports it but I want your confirmation as I still don't have HW to test and don't want to change the package again and redo the HW.Thanks,Ayoub  

Question moved from the knoowledge base article: How to use STLINK-V3 MCO output on Nucleo boards as a precise clock source for STM32 Hello,  With this method, what level of accuracy (PPM) is expected ?   Thank you and have a good day.  

Hi Team, I am working with the STM32N6570-DK board and reviewing the available power measurement methodology. From what I understand, the current approach/documentation focuses on measuring only VDD_CORE power. My requirement is different: I want to measure the total MCU power using a JS220 Joulescope, not just the VDD_CORE domain. Specifically, I would like to understand: What is the recommended hardware measurement point on the STM32N6570-DK board to capture total MCU power? Is there a board jumper, shunt, or power rail that isolates the complete MCU supply path? If measuring only VDD_CORE is the officially supported method, what additional rails should be included to estimate total MCU power? Has ST validated any method for measuring full MCU consumption on this board, including CPU, NPU, internal memories, and essential MCU peripherals? Are there any precautions regarding ST-LINK, external memories, camera/display rails, or other board circuitry

Hi everyone, I am encountering a critical issue with the IWDG on an STM32U375 using STM32CubeMX v6.17.0 and a Segger J-Link Base. The scenario: I am testing the Watchdog behavior across Standby cycles. I have configured the Option Bytes via software to freeze the watchdog during low power modes: IWDG_SW: 1 (Software mode) IWDG_STOP_FREEZE: 0 (Counter stops in Stop mode) IWDG_STDBY_FREEZE: 0 (Counter stops in Standby mode) The Issue: When the system is in IWDG_STDBY_FREEZE mode, the following happens: The MCU wakes up from Standby correctly. I enter a test while(1) loop without refreshing the IWDG. At the exact moment the IWDG timeout should occur (10s), the MCU enters an unrecoverable state. No System Reset occurs. No HardFault_Handler is triggered. The CPU seems to be completely locked (Bus Lockup?). I tried to enable the IWDG Early Wakeup Interrupt (EWI) via NVIC, but HAL_IWDG_EarlyWakeupCallback() is never called before the crash. Contrast with RUN mode: If

I'm failing to enable that Interrupt using " LL_RTC_EnableIT_SSRU(RTC) " on STM32H33.Wakeup timer is set to interrupt every 24h (this is working).Alarm A is configured, but not enabled.Alarm B is not used.RTC is set to BCD mode only.Monitoring SSR register ( via "READ_REG(RTC->SSR)" ) I can see it's counting down from 0xFF ---> 0x00, periodically.Some Internet folks told me to enable TAMP Interrupt as well...and intercept TAMP IRQ handler instaead of RTC IRQ handler. It didn't work.Any help would be greatly appreciated.Thanks.    

Hello everyone,here are my questions:1. Is there any roadmap or community effort to add NeoChrom/GPU2D support to Zephyr?2. Has anyone successfully integrated the STM32 HAL GPU2D driver alongside Zephyr?3. Would it be possible to:- Initialize GPU2D using HAL in the Zephyr application- Patch Zephyr's LVGL Kconfig to expose Nema GFX options- Use LVGL's existing lv_draw_nema_gfx_stm32_hal.c backend4. Are there any technical blockers (interrupt conflicts, clock management, memory mapping) that would prevent this hybrid approach?I'm willing to contribute if there's guidance on the proper implementation approach.Thank you for any insights.

Hello, all my tools are updated to last ones, and software packages too. I start an empty project using X Cube FreeRtos 1.5 (just a default task). Play the soft with debug, and after a few seconds, press "Suspend" button to break the running program. Then, there are a lot of calls to vPortSetupTimerInterrupt function (port.c) in the call stack. The tick is by default 1ms and cpu clock to 250Mhz.  Not sure that is normal? thanks for your help Laurent    

Is FP32 forcing software kernels and preventing NPU acceleration? Hi,I am testing CIFAR-10 ResNet on STM32N6570-DK and I need help understanding a latency gap between two STEdgeAI generation flows.I used the same FP32 model as input:CPU-only generation flowCPU+NPU generation flowBoth flows generated C files and hex successfully, and both run correctly on target.However, the CPU+NPU build is significantly slower than CPU-only.What I would like ST to confirm:For STM32N6, can full FP32 ResNet graphs be truly accelerated on Neural-ART, or are they generally expected to run as software float kernels?Is it normal that CPU+NPU generation for FP32 can be slower than CPU-only generation?For real NPU acceleration, is calibrated INT8 mandatory in practice?Which exact generator settings should I use to ensure that most layers map to NPU kernels (and how to verify mapping from generated artifacts)?Observed latency:CPU-only flow: about 211 msCPU+NPU flow: about 439 msMy main question:Is this ex

Hi all,What is the recommended way to not crush our repository and dynamically pull/generate the project's Drivers and Middleware folders?  For instance, our repository has both Bootloader + Application code projects in a repo (and other MCU projects/layouts for the same board).Is there something similar to Platform.IO (or C#'s NuGet packages) where the platform maintains those 3rd-party files in a volatile location and pulls them if they don't exist on your machine? Especially for the sake of not checking into the repo duplication of +15 MB worth of files for each project.Please excuse me if this was already asked. I didn't quite find a solid answer.I'm ok with making a command line script that auto-pulls them too, if that's a possibility.

Hi,I do not plan to use USB or CSI, and the board only receives 1.8V power. So, I asked how to connect the VDD33USB pin, and I was told to just connect it to GND. However, I have two more questions.I currently have the VDDA18USB and VDDA18CSI pins connected to 1.8V. Is it okay to leave them as they are, or would it be better to connect them to GND? (have to consider leakage in the Stop mode)Also, should I connect VDDCSI to GND as well?Thanks in advance.

Hi, will ST extend I-CUBE-LRWAN support to include the new MuRata LBAA0QB1SJ-TEMP-EVK? Or offer a ST board based on LBAA0QB1SJ-295? Any suggestion on how to reconfigure the current I-CUBE-LRWAN version to work on the new EVK? We were previously using B-L072Z-LRWAN1. 

I am struggling with getting a STM32mp25D board flashed, it hangs at BL32 (see output below). It does have one warning "WARNING: Could not enable VRSEL for vddio2", but I don't think that is relevant to the hanging at BL32 (but I could be wrong). I have successfully flashed a STM32mp25F-EV1 board, that works fine. Seeing as the difference between the D and F flavor is that F supports secure boot, I have attempted to tweak OPTEE settings, such as building  OP-TEE OS with configuration CFG_STM32MP_PROFILE=system_services, as suggested here. I have also attempted to set BOOTSCHEME_LABELS = "opteemin" in the boot scheme section of the stm32mp25.conf file. Someone else on the team is also tweaking firewall/security settings, also with no success. I'm not sure exactly what they have attempted on that front, however. I am wondering if someone else has run into this problem/has a solution? I'm also unsure if I'm barking up the wrong tree thinking that the issue lies with OPTEE/f

Hi!I am working on the STM32MP257F-DK board for a robotics project. For this, I want to map some of the GPIO to M33 in order to control the motors while the Linux of the A35 will run the ROS software. From what I understood is follows:I need to customise the device tree to give the permissions of the GPIO to M33 (I initially tried directly flashing with a STM32CubeIDE project and the mpu got reset)I need OpenAMP to communicate between the processors (A35 needs to send calculated moves to M33)How to achieve it I am not sure and I am unable to do it. I went through the STM resources but I am finding it quite confusing.I have installed the Developer-Package, Distribution-Package and Starter-Package as given in following documents:https://wiki.st.com/stm32mpu/wiki/Getting_started/STM32MP2_boards/STM32MP257x-EV1/Develop_on_Arm%C2%AE_Cortex%C2%AE-A35/Install_the_SDK https://wiki.st.com/stm32mpu/wiki/STM32MPU_Distribution_Package#Installing_the_OpenSTLinux_distribution https://wiki.

Hi,I'm experiencing a fetching error with m4projects-stm32mp1 while building st-image-weston.First i had problem while fetching from:git://github.com/STMicroelectronics/STM32CubeMP1.git;protocol=https;branch=masterSince github doesn't support git: protocol anymore i changed that to https.But i still have fetching errorERROR: m4projects-stm32mp1-1.7.0-r0 do_fetch: Bitbake Fetcher Error: FetchError('Unable to fetch URL from any source.', 'https://github.com/STMicroelectronics/STM32CubeMP1.git;protocol=https;branch=master')I can clone this repo manually but yocto doesn't.Cloning that takes some time (about 2 minutes) but yocto fails quickly. Seems it doesn't even tries to wait fetching to finish.Are there any thoughts how to solve that?

As i updated my STM32CubeIDE to the latest site version available, i am getting new errors in my working code.Those errors before update were displayed as warnings but after update they are turning into errors. passing argument 2 of 'xfunc' from incompatible pointer type [-Wincompatible-pointer-types]My -Werror is unchecked from the start.If someone can help me how to resolve it, Thanks in advance.

SummaryI'm attempting to add support for a custom STM32MP135-based board (M5Stack CoreMP135) to Yocto using meta-st layers, but the u-boot-stm32mp recipe appears to enforce rigid constraints that prevent using custom defconfigs and device trees. Environment- **Yocto Version**: Kirkstone- **meta-st Version**: OpenSTLinux 5.0 (Kirkstone)- **Target Board**: M5Stack CoreMP135 (STM32MP135DAE7, 512MB RAM)- **U-Boot Version**: v2022.10-stm32mp-r2- **Reference**: M5Stack successfully builds this board with Buildroot using custom defconfig Problem Description What Works in BuildrootM5Stack's Buildroot configuration successfully builds U-Boot for the custom board using:```BR2_TARGET_UBOOT_BOARD_DEFCONFIG="coremp135"BR2_TARGET_UBOOT_CUSTOM_DTS_PATH="$(BR2_EXTERNAL_ST_PATH)/board/m5stack/coremp135/uboot-dts/*"BR2_TARGET_UBOOT_CUSTOM_MAKEOPTS="dtb-y=stm32mp135f-coremp135.dtb DEVICE_TREE=stm32mp135f-coremp135"``` Attempts in Yocto (All Failed) Attempt 1: Using UBOOT_MACHINE Override**Machine config:

Hi all, There are a few options for mp3 decoding but none seem to be for the M33 core MCUs. Source code seems to be missing too: X-CUBE-AUDIO: the precompiled binaries only seems to support M4 and M7 cores.X-CUBE-AUDIO-KIT: this does not natively have an mp3 decoder.STM32-MP3NL/DEC: this looks like a precompiled spiritmp3dec file for M7. I've spend too many hours looking into this and I'm back to where I started. It looks like the best option would be to use X-CUBE-AUDIO-KIT and add an mp3 decoder to audiochain but how? it needs to support the M33 core and ideally have the source code available. I've also read that some people here have used minimp3. I prefer an option supported by ST and I'm not sure that is the case. Comments/suggestions welcome. Thanks.

Hello @INaee.1 , I am working with the STM32H743BIT6 using the LTDC peripheral to drive an RGB display. The display I am using does not have HSYNC and VSYNC signals and operates only in DE (Data Enable) mode. I have attached the display datasheet and pin connection for reference. Based on the datasheet timing specifications, I configured the LTDC parameters accordingly. Since the display does not use HSYNC and VSYNC, I configured them as constant high signals (logic 1) and set the rest of the LTDC timing parameters as specified. However, the display is not showing any image. The backlight turns on, but the screen remains black. Below are the key points of my configuration: LTDC peripheral configured according to the display timing parameters from the datasheet HSYNC and VSYNC set to constant logic high since the panel works only in DE mode Pixel clock configured as per the display requirements Data Enable (DE) signal connected and

Dear all,We have a design where the VCCQ of eMMC is currently 3.3V. We need to move to 1.8V to be able to use a new referenceIs there any risk to break somthing if I use the below DTS on board where eMMC is 3.3V VCCQ. We have pull up to VCCQ on D0 and CMDvqmmc-supply = <&v1v8>; mmc-ddr-1_8v;According to my tests, system is up and running, but I fear this should have an impact on MPU padsIf no risk, this could avoid me to add a DTS overlay according to my hardware board version in case of 3.3V VCCQI add my layout for eMMC for better understanding, see R353 and R356 to switch VCCQThanks in advance for answers and hintsRegardsLaurent  

I'm working on a project using the STM32U385 and I'm trying to find a way to detect a specific condition and save data while the device stays in a low-power Stop mode — without waking up the CPU to do the saving.Is there any peripheral combination or hardware feature on the STM32U385 that allows:1. Detecting a condition (e.g., via Comparator, ADF, or LPTIM) while in Stop mode2. Saving/writing data to memory autonomously — still in Stop mode, without waking up the CPUIf this is not possible natively, is there a recommended approach or workaround for this use case on the STM32U3 series?Thanks in advance!

Hi Team  I am trying to do UART bootloader, using cli command. The MCU used is STM32F446RET6 and dev kit used is nucleo-f446re.I am using USART1, for printf and cli command with interrupt. CLI command is used to enter system memory /bootloader but as shared above the programmer is not giving timeout error.   void jump_to_bootloader(void) { void (*SysMemBootJump)(void);   //system address defined volatile uint32_t addr = 0x1FFF0000;   // //introduce delay before switcing to bootloader after printf. // HAL_Delay(200);   //disable all interrupt request and stop SysTick __disable_irq(); // SysTick->CTRL = 0; // SysTick->VAL = 0; // // __HAL_RCC_SYSCFG_CLK_ENABLE(); // SYSCFG->MEMRMP = 0x01; //Deinit HAL and all peripheral   // HAL_UART_DeInit(&huart1);   //reset uart pins and gpio // __HAL_RCC_USART1_FORCE_RESET(); // __HAL_RCC_USART1_RELEASE_RESET(); // HAL_GPIO_DeInit(GPIOA,GPIO_PIN_9 | GPIO_PIN_10); HAL_RCC_DeInit(); HAL_DeInit(); // D

Hello,I am trying to use the newest cmsis dsp library (v1.15) to implement a vector matrix implementation. I am running into a "first defined here error" when trying to build with the cmsis dsp library (v1.15). I created an empty project just to try out building a project with the library included. I am running into the same issue there.I am using STM32CubeIDE version 1.13.1 and an STM32H750 with an M7.If I understand correctly, CMSIS v 1.15 does not have a "lib" folder anymore like the older versions and only the Include, PrivateInclude and Source folders must be integrated. Therefore the instructions in Configuring DSP libraries on STM32CubeIDE - STMicroelectronics Community are not helpful to me.Here you can see the folders I included. Am I missing something? How can I use the newest CMSIS library? I couldn't find any helpful documentation on the internet.Thank you,Leonard

I am implementing a secure boot process on the STM32H723. My application has three firmware components with the following memory layout:1. BOOT: Located in internal Flash.2. OS: Located in internal Flash.3. USER: Located in external SDRAM.The required boot and runtime behavior is:1. Upon power-on, the BOOT code must read and perform a full verification (e.g., checksum, hash) of the entire OS image from internal Flash.2. After verification, the BOOT jumps to the OS.3. The OS provides a runtime environment for the USER application. The OS and USER application need to interact bidirectionally (e.g., call each other's functions).Core Security Requirement:The USER application (running in SDRAM) must be prevented from reading the code of both the BOOT and the OS from internal Flash. The OS code should be executable but not readable.Question / Request for Clarification:The PCROP (Proprietary Code Read Protection) feature seems designed for "execute-only" protection. However, a conflict exists