STM32 MCUs Products

Hello,Document: RM0090 Reference Manual for STM32F405/415, STM32F407/417, STM32F427/437 andSTM32F429/439.https://www.st.com/resource/en/reference_manual/rm0090-stm32f405415-stm32f407417-stm32f427437-and-stm32f429439-advanced-armbased-32bit-mcus-stmicroelectronics.pdfRevision: 21, 07-Jun-2024.Location: Pages 847-862 in Section 27. Also, Figure 241, 242, 243, 244, 245, Table 125.This section, figures and table all contain 17 references to ITEVFEN bit, supposedly from I2_CR2 control register.In reality, there is no such bit in this register, the actual name is ITEVTEN (interrupt event enable), and it is located in I2C_CR2, bit 9.Section 27.6.2 has correct name.stm32f405xx.h file, and others related to i2c, use the correct name: #define I2C_CR2_ITEVTEN_Pos (9U) #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */Therefore, the ITEVFEN in the document should be repla

Hi,I'm working on STM32N6 with CubeMX + X‑CUBE‑AI to deploy a neural network model.The first AI model works fine: no compile errors, runs normally.When I replace the neural network model in CubeMX and regenerate code, I get dozens of compile errors (undefined reference, multiple definition, missing files, etc.).Clean project in IDEDelete build / Objects / Listings foldersReimport the new model in CubeMXRegenerate code completelyI have tried:But the issue still exists. It seems old AI files are not cleaned properly when changing models.Has anyone faced similar issues on STM32N6 when switching AI models with CubeMX + X‑CUBE‑AI?How did you solve this? Thanks for help.

Hi everyone,I am currently looking into the STM32F303CCT6 and I'm a bit confused by the ADC specifications. ST's website mentions it can achieve up to 18 MSPS in interleaved mode. However, looking through the Datasheet and the Reference Manual (RM0316), I don't see a clear way to hit 18 MSPS at 12-bit resolution.I realize the hardware interleaved mode is only dual (e.g., ADC1/2 and ADC3/4). Since the documentation mentions dual mode can reach up to 9 MSPS at 12-bit, and there is no native quad-interleaved mode, I suspect one of two things:There is a way to manually coordinate the two dual pairs (using all 4 ADCs) to reach 18 MSPS at 12-bit.The 18 MSPS claim strictly refers to running a dual interleaved setup at a reduced 6-bit resolution.I would deeple appreciate some insight regarding if 18 MSPS at 12-bit is actually possible on this MCU, or if I am limited to the dual mode specs?Thanks in advance!

Hi,We are currently using STM32H753 and are setting up USB Fifos. There is some contradictory information about the available sizes. AN4879 mentions that the available SRAM size is 1.25kBytes for OTG_FS:In the reference manual RM0433 I can only find 4kB for both OTG_HS peripherials, where OTG_HS1 is used for OTG_FS:What information is correct?Thanks and best regardsDaniel  

Hello,I am trying to use the I3C interface between STM32H523 and DDR5 SPD. I have found a question would like to be answered: Is there any way to send the broadcase address (7'h7E) with SCL signal configured in I2C timing characteristics?According to MIPI I3C Basic specification v1.1.1, page 366, Table 86 I3C Open Drain Timing Parameters, note 9,The Controller uses this timing to send the first Broadcast Address after Bus initialization, in order to disable the I2C Spike Filter for applicable I3C Target Devices (see Section 5.1.2.2.2) (At least 200ns)I have selected the "Bus Characteristics" as "Mixed I3C and I2C" and "I2C Duty Cycle" to be 50% in stm32cubeIDE's "Pinout & Configuration -> Connectivity -> I3C1", It generates the code with "hi3c1.Init.CtrlBusCharacteristic.SCLI2CHighDuration = 0x7c;", which seens fine. But when I run the function "HAL_I3C_Ctrl_TransmitCCC", I found the waveform is different, the SCL high duration is actually controlled by th

I'm reading RM0492 Rev 3 about I2C's controller transmitter. The original words on the page of 1185 areWhen RELOAD = 0 and the number of data bytes defined in NBYTES[7:0] is transferred: • In automatic end mode (AUTOEND = 1), a STOP condition is automatically sent. • In software end mode (AUTOEND = 0), the TC flag is set and the SCL line is stretched low, to perform software actions: – A RESTART condition can be requested by setting the START bit of the I2C_CR2 register with the proper target address configuration and the number of bytes to transfer. Setting the START bit clears the TC flag and sends the START condition on the bus. – A STOP condition can be requested by setting the STOP bit of the I2C_CR2 register. This clears the TC flag and sends a STOP condition on the bus. When a NACK is received, the TXIS flag is not set and a STOP condition is automatically sent. The NACKF flag of the I2C_ISR register is set. An interrupt is generated if the NACKIE bit is set. I'm co

Hi , I have developed a testcase where STM32H503 i3c is in target mode, requesting for controller role request that is going to controller (checked interrupt - Secondary Controller received Controller Role Request ) . After controller is sending GETACCCR command to target but in target side I3C_EVR.CCRUPDF bit is not set. Can you please guide me how to check CRR request. 

This is looking for more info from this original post * https://community.st.com/t5/stm32-mcus-embedded-software/i-am-using-usb-pd-system-with-stm32g071rb76-processor-there-are/m-p/219760#M53483     With a stm32 chip with only one CC line could i connect both of the CC lines together. This is a DFP I don't need VCON support If i were to do this could i still figure out what the orientation is?  

Hi, I’m trying to configure the FDCAN peripheral on a NUCLEO-STM32H72ZG board, but even though it works perfectly in loopback mode, it doesn’t work when I switch to normal mode. Even in external loopback, when I check with the oscilloscope I don’t see any activity on the TX pin (no signal transitions). The same issue occurs on this board also with GPIOs. I tried the same setup on a NUCLEO-STM32F303RE board (using CAN instead of FDCAN), and everything works perfectly there.      

Dear all,I'm implementing Over-the-air firmware updates for a board using the STM32N657 MCU.In the Appli, I download the new firmware binary over Wifi and store it to RAM at a fixed location in AXISRAM5 and 6. In order to flash the new binary to the OctoSPI Flash I prepend a "magic" header to the new firmware binary (still in RAM) and then restart the MCU using `HAL_NVIC_SystemReset`. Then, after this reset the FSBL checks the fixed location in RAM for the "magic" header. If present, it should flash the OctoSPI Flash with the new firmware binary using the ExtMem Manager (I cannot just flash directly from Appli because I use XIP and hence the Appli is running from OctoSPI in memory-mapped mode, preventing writes). I've done similar things with other MCUs and it worked perfectly fine.However, it looks like on the STM32N6, the contents of AXISRAM5 and 6 are not preserved across software resets. At least, checking the "magic" header in FSBL always produces randomly looking results that are

Heyho,I recently found that I'm not using ITCM RAM at all, then started to put heap and stack there.No problems so far.Then I copied some functions there, and all went well - until I found some strange behaviour:1..4 SAI RX DMA transfers running, circular modewhen all these transfers are complete for each SAI, a function is called to copy the complete DMA buffer from internal AXI SRAM into the big buffer in HyperRAMalso in this function a packet counter (a global u32 in DTCM) is incremented oncebut when this function is in ITCM, this packet counter increments for each SAI active, but there are no extra packets Further info:- instruction cache: in use- data cache: not used Is there any guideline what to put in ITCM, what are the limits, etcpp. ?

hello, where can i download win11 STM virtual com port?  i install both VCP_V1.5.0_Setup_w7_x64_64bits and W8_x86_32bit all not working ! i din seeSTM Virtual Com port at device manager! only STM STLink visual com port appear ... 

Hello,in our design with STM32H753ZIT6 I've adjusted the C0G load capacitors on the LSE 32.768 kHz crystal so that the real-time clock is now very accurate (less than 1 second error in 24 hours). I've always performed the calibration in VBAT mode at a voltage between 2.3 and 3.2 V.However, now I've noticed that in normal VDD mode with active controller, the real-time clock is running significantly too slow, with an error of 90 seconds in 24 hours. I've ruled out the VBAT supply voltage as the cause. Any ideas what could be causing this large error in normal VDD mode?Thank you!

Hello i use STM32G070CBT6 with PD0 and others pins.PD0 as input pin with no internal pull-up/down with extrenal 10k pullup gives only 0.7V, when i set the pin to output and set state to high there is 3.3V.Where is the problem? 

Dear ST Community,I am currently migrating my Firmware from STM32H723VG to STM32H563VI. I have problem with Internal Temp Sensor. Based on Reference Manual on both MCU reading temperature is the same, but it doesn't work as it should.When on STM32H7 I got about 750 (24 degree Celsius) on reading ADC from TEMP Sens, on STM32H5 I have around 100.I tried both with and without cache (ICache and DCache), with Bare Metal and Zephyr RTOS code. In every configuration it is not working. I tried also on different MCUs, so it shouldn't be part itself.It worked with Nucleo H563ZI, but doesn't with H563VI.What else can I do?

Hello,I want to change for boot to use XSPI1 interface, but I am not sure about OTP bits, there in description some bits is not very clear, what OTP bits to set to switch if it's possible ?Additionally if I will use SD card for boot I can set OTP11 value to 0x00000020 (bit5 = 1 = sdcard), write FW to sd and use sd for boot source ?Thanks.

Say I am operating as master with CPOL=1.  Because the NSS pin seems to lag the enable bit (SPE) slightly, my logic analyzer always barfs on the first SPI packet because the clock is in the wrong state.So, I set the GPIO to have a pullup on the clock in CubeMX and the problem goes away - as soon as the init functions run, the clock goes high and stays that way until the first SPI transmit.  Also, the clock stays high after the end of the transfer if the SPI is disabled in the callback function.My only concern is for power consumption: It is obvious that the pullup gets applied when the SPI is disabled but I don't know is if the pullup applied all the time even when the alternate mode of the GPIO is set, i.e. is the pullup still applied at the pin when the SPI is enabled?  Do clock pulses during an SPI transaction work against the pullup? 

I'm working on a design with an STM32L072CZT6TR, where I want to calibrate my main timebase. That main timebase is TIM6, which counts 16,000. The HSE is 16MHz, so there's an interrupt evey 1ms. Calibration is done by counting the number of HSE cycles between two consecutive PPS pulses from a GPS receiver. The PPS triggers an EXTI interrupt, which starts TIM21 and TIM22 at 0 on the first pulse, and reads the timer values on the second.TIM21 is set to count 16,000 pulses and TIM22 is slaved to TIM21. This way, I can conveniently determine whether the HSE is slow (TIM22 == 999) or fast (TIM22 == 1000), and calculate a correction based on TIM21.This logic is copied straight from an older design with an STM8, where it works like a charm. However, the cascading does not work. No matter what, TIM22 is always 0 on the second PPS. I have used CubeMX to set the timers up, and, going over the code with the reference manual as my guide, I can see no errors. Being a hardware engineer

Hardware & Setup- MCU: STM32H523RE (I3C target/slave mode) - Controller: STM32H533RE (I3C controller mode)- HAL Version: STM32CubeIDE 1.16.1, HAL for STM32H5- Bus Speed: 3.205 MHz I3C SDR Problem Description We're implementing an I3C target that needs to respond to random address reads with repeated start: [START][ADDR_W][0x01][RESTART][ADDR_R][DATA][STOP] Where:- ADDR_W writes the address byte (0x01) to tell the target which register to read- RESTART signals the repeated start- ADDR_R begins the read phase- Target should respond with data from address 0x01 The problem: Loading the TX FIFO in the RXFNE interrupt handler doesn't work. The hardware transmits stale data before the ISR can fill the TX FIFO with the requested data. 1. RXFNE interrupt fires when address byte (0x01) is received2. ISR starts executing (~1-2µs interrupt latency)3. ISR flushes TX FIFO and writes fresh data to TDR registers4. But hardware has already started transmitting from the (empty/stale) TX FIFO The I3C

Hello,I’ve recently started using ST products and the IDE with CubeMX, which is why I’m asking for your help. I’ve just begun developing a communication system using a Nucleo H743ZI2; my goal is to set up a UART and a CAN bus.The UART is done; I used DMA access to optimize it. However, when I try to enable the CAN bus in Cube MX, I run into a problem with the clock configuration related to the bus.When I use the “Resolve Clock Issues” function, I get the error: “Cannot find a solution for some constraints.” Does anyone have any ideas to help me solve this problem? Thank you in advance, and have a great day,

For STM32H7, if the FMC data lines and SDRAM data lines are cross-connected (not D0 to D0), and address lines are also cross-connected (not A0 to A0), can SDRAM work properly? My PCB is about to be manufactured, but due to the hardware engineer’s design, the SDRAM data lines and the MCU’s FMC data lines, as well as the SDRAM address lines and the MCU’s FMC address lines, are not connected one-to-one according to the CubeMX standard. Instead, the order has been shuffled. The actual wiring relationships are as follows: Data line connections: MCU FMC_D0 is connected to SDRAM_D13MCU FMC_D1 is connected to SDRAM_D14MCU FMC_D13 is connected to SDRAM_D1MCU FMC_D14 is connected to SDRAM_D0MCU FMC_D4 is connected to SDRAM_D7MCU FMC_D5 is connected to SDRAM_D6MCU FMC_D6 is connected to SDRAM_D5MCU FMC_D7 is connected to SDRAM_D4Address line connections: MCU FMC_A0 is connected to SDRAM_A2MCU FMC_A1 is connected to SDRAM_A3MCU FMC_A2 is connected to SDRAM_A0MCU FMC_A3 is connected to SDRAM_A1MCU

According to the PD 3.1 requirements (also PD 3.0), I need to connect UCPD1_CC1 and UCPD1_CC2 to USB-C CC1 and CC2 to communicate and request the desired voltage. But STM32G0B1KBU6  has only UCPD1_CC1 available. Is there any way to connect STM32G0B1KBU6  to USB-C to comply PD 3.1 requirements?

Hello,the SPI does work with NSSP(Negative Slave Select Pulse-Mode), but it does not work if I disable NSSP. As someone pointed out the SPI NSS(P) may only work if the Pulldown of that pin is enabled, but I’m not 100% sure on that one, but it seems to wirk for NSSP-En that way. For NSSP-Disabled I could not get the SPI-Controller to control the NSS(CS).I observed two issues:1) On Reset the NSS(CS) is low and will stay low until the first SPI Transaction. I tried to set it via HAL_GPIO_WritePin( … , GPIO_PIN_SET); but that has no effect, maybe because the Pin is controlles by the SPI-HW.2) Is the serious issue is, if I disable the NSSP, the CS does not work at all.How can I make the Hardware NSS work with NSSP disabled?Thanks a lot, Best Regards, SeppelP.S.This is the Setup and Waverforms for the NSSP-Disabled, I have a 2s delay on startup, which you can see on the scope-pictures.: This is the setup for the NSSP Enabled, the same was used for NSSP-Disabled(only that NSSP was set to

Hi,is there any HW guidelines to configure a USB OTG port with STM32H563VIT6 with VBUS detection?

Hello.I recently experienced an unusual MCU Problem and need to analyze it. Please help me. The FW program download to the MCU is successful, but it does not operate after a reset. I performed a short circuit test after disconnecting the power(Battery)but even when measuring VCC-GND and GND-VCC at the power supply, a resistance value of approximately 500 ohms is detected. When I disconnect only the MCU from the PCB and re-measure, the 500 ohm value disappears from the PCBbut this value persists when measuring directly from the MCU pins. Can I conclude that the MCU is dead due to a power supply failure?And in what cases does this problem occur?