STM32 MCUs Products

I am currently using the STM32F446ZET6 chip, which comes with 16MB of off-chip SDRAM. I have been trying to run the program in the SDRAM, but have not been successful. I would appreciate any help.

In STM32F413VGT I2C3 support Fast Mode Plus(1MHz)?I cannot find documentation

Hi!I am experiencing some confusing behaviour on an STM32H743 series chip:I am running an injected ADC channel on ADC2, with trigger from the HRTIM. The HRTIM is triggering at 8000 Hz (200 MHz clock, prescaler div-2 and period = 12500). The ADC generates an interrupt at injected end-of-conversion, with 64.5 cycles per sample in 16-bit mode. The ADC clock is running at 80 MHz, with prescaler div-4, i.e. 20 MHz.  When setting an oversampling ratio such that the conversion time becomes longer than the time between the trigger pulses, I always get half the expected frequency for the generated interrupts. For example, with oversampling ratio 64, I can calculate the conversion time as:t_conv = (64.5 + 8.5) * (1 / (20*1e6)) * 64 = 0.2336 mswhere the 8.5 extra cycles come from the fact that we are in 16-bit mode as per documentation. From this, the ratio between the conversion time and the time between two consecutive trigger pulses is about 2, i.e. for each conversion

Hello We are working on a new project with STM32H723ZGT6. I want to control S70KL1283DPBHI020 DRAM with HYPERBUS communication using OSPI1. If you access 0X900000 memory to write and read data during the current operation, the data will not be read accurately. It seems necessary to check if there is a problem in the circuit diagram. I'm using PC2_C pin and PC3_C pin for IO5,6, is it not a problem? Is it not a problem to use the RESET PIN as a GPIO OUT PIN to give a HIGH signal I gave the data a value of 0xff up to 100 bytes, but there is another value in the 4th address. I would like to ask you to check the problem. Thank you.

Hello everyone. I read that V8 will become available for OEM in Q1, but is there any estimations when V8 will become available for independent engineers or maybe even NUCLEO V8 will be released?

Hello,In our application there is a STM32L073CZT3 component, we use timers and DMA to generate PWM that simulates a sine wave to start a motor.We encounter a problem with the microcontroller at high temperatures (about 80 degrees Celsius and above).The microcontroller stuck in all sorts of different states, sometimes the DMA and timers continue to work but the communication and control(PID) stop running in the background, sometimes everything stops (the external clock continues to work at 24MHz), and sometimes the DMA interrupts stop working for a few milliseconds (1-7msec)  and then start working again (which produces a reset in our case as a result of a return current from the motor, and a protection component that disconnects power to the circuit). Can you help with ideas why this is happening to us? Thanks,Oren Shoef.

Hello.   I'm having a problem with an STM32H503. I need to use the RTC, which is running on the internal 32kHz LSI clock. The clock configuration was created with CubeMX.   When I check the RTC, I see that it has only advanced by 21 seconds in 60 seconds. That's a deviation of 285%. The processor is running on the HSI clock, which is divided by 2, so 32MHz. Does anyone know why the RTC is running 3 times too slow?   Init of the RCC: RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // RCC_PLL_OFF; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLO

 It's across 'U5, 'H5, 'H7 RMs, maybe more.How did I spot that? I was text-searching for 'NMI' ... :)JW

Hello ,I want to Access QSPI drivers in STM32H7A3VIH6. However in Cubemx there is only option of OCTOSPI1 and OCTASPI. My question is there way to use QSPI api directly like HAL_QSPI_Init instead of OSPi init?Or we have use OSPI only?Secondly i am using 2 external flash to be used in each QUAD SPI.

Same issue reported in 2020: https://community.st.com/t5/stm32-mcus-products/stm32g473-fdcan-pinout-contradicting/td-p/224770.As of DS12712 Rev 5, Table 13 Alternate Functions has PB10 and PB11 mis-labeled as FDCAN3_RX and FDCAN3_TX respectively.Under AF11, PB10 and PB11 are not available as FDCAN3_RX and FDCAN3_TX.

Hello ST community,I am working on an application on STM32N6570-DK using the camera to detect humans with an AI model (X-CUBE-AI + NPU) and draw bounding boxes on the LCD using LTDC.I am facing a display corruption / glitch issue that only appears under very specific conditions, and I strongly suspect an AXI / interconnect / NPU side effect, possibly related to an undocumented reset or QoS state.Project architecture:Camera -> DCMIPP -> PIPE1 -> BUFFER1 -> LTDC_L1                                 -> PIPE2 -> BUFFER2 -> NPU -> Config ROI of DCMIPPMemory placement:LTDC framebuffer: AXIRAM2AI input/output buffers: AXIRAM5No buffer sharing between LTDC and AIProblem description:When MX_X_CUBE_AI_Process() is commented, the camera preview is perfectly stable on the LCD.When MX_X_CUBE_AI_Process() is enabled, continuous display glitches appear (tearing / corrupted lines).The issue happe

In the FD_CAN register, there is a CEL[7:0]:, REC[6:0]: and TEC[7:0]:,The CEL register is not being reset on read and goes into the Bus-Off mode.Do I need to also reset the REC and TEC register?I am currently using the HAL_GetErrorCounter() function to read the register. 

Hello all,I have a custom board using an stm32h747bit6. I am able to flash it and it works exactly as intended, but if I power cycle it then it stops working?  If I flash it and then reset the chip it still works fine.I tried some debugging, I configured the error handler to toggle a gpio pin on / off but it doesn't do that, the voltage just sits at ~0.8v after I power cycle it? Any ideas?

I would like to ask if there has been any change in the screen printing of STM32L433RCT6 from Taiwan, as the Z next to the ARM in the first line is not close, while the Z next to the ARM in China is close. As shown in the following figure.

Hi,Ref.manual (RM0477 Rev 8) in chapter 32.3.3 PSSI clock saysIn case when PSSI transmitting data, then RDY pin is input.Datasheet (DS14360 Rev 2) shows setup and hold time of RDY pin (input) referenced to rising edge as well as data pins (outputs).I think that's a contradiction. So how is it really and to which edge do RDY setup and hold times relate ?Thanks,Michal Dudka

Hello everyone,I am currently working on a project using the STM32F030C, and I have a question regarding the GPIO speed configuration (slew rate) for SPI pins.Here is my setup:MCU: STM32F030CInterface: SPI (configured as Slave)SPI Clock Frequency: 13.5 MHzTo keep EMI (Electromagnetic Interference) emissions as low as possible, I was considering setting the GPIO output speed for the SPI pins (specifically MISO, since the MCU is the slave) to GPIO_Speed_Level_Low.However, according to the datasheet (see attached screenshot), the "Low" speed setting is specified for a maximum frequency of 2 MHz.My questions are:Is it practically possible to run a 13.5 MHz SPI signal with the GPIO speed set to Low, despite the datasheet specs?Does this pose a high risk of corrupted/poor communication due to the slew rate being too slow (e.g., degraded signal integrity, failing to meet setup/hold times for the master)?Has anyone here tried this approach to reduce EMI at similar frequencies, or is it strictl

HI, I am using STM32H745BIT6 ST controller in my custom board.Configured in Direct SMPS mode. When the board is powered on the VCAP voltage is 1.2V and settling at 1V as expected when we try to flash the program to controller the voltage is same, but when we are trying to enter into debug mode the voltage is dipping from 1V to 0.6V and after 5uS its coming back to 1.2V.( Image is attached for reference)Due to this issue, I am not able to enter to debug mode controller is getting disconnected and showing the pop-up as TARGET IS LOST. I have taken all the precautions mentioned in datasheet and reference manual.1) Shorting all three VCAP pins.2) Connected two 2.2uF capacitor near to the pins.3) Even tried with higher capacitor value.4) Checked the shorts in the pins and board with the help of multimeter.5) The PWR_CR3 register is also set to Direct SMPS mode and verified the last 4 bits as 0100.6) Verified in the IOC that it is configured to Direct SMPS

Hi everyone,A slightly different topic from the usual embedded discussions, but something many working professionals here might relate to.For those balancing engineering careers and parenting, choosing the right daycare can be a major decision — especially for infants and toddlers (0–3 years old). While researching options for a licensed infant daycare near Edmonton AB, I noticed that many centers now incorporate structured early learning programs, digital communication systems, and real-time parent updates.It made me curious from a tech professional’s perspective:How important is licensing and regulatory compliance compared to reviews?Do you prefer daycare centers that use digital parent apps for daily updates?Does structured early development curriculum matter at the infant stage?Have you seen technology (monitoring systems, check-in/check-out systems, reporting dashboards) influence your decision?Many of us work in fields where safety, reliability, and compliance are non-negotiable.

Greetings, I am working with the STM32U585RI and a sensor that asserts an interrupt on the MISO line. I would like to know whether this setup is feasible, and if so, how best to implement it. One approach I have considered is to use a separate pin (LPGPIO) to monitor the interrupt condition and then trigger the SPI sequence. However, during ongoing SPI transactions, I would need to temporarily disable the interrupt feature and re‑enable it after each transaction. My question is, how can this be achieved using LPBAM? Is there a recommended way to configure LPBAM so that the interrupt handling and SPI transfers can coexist without conflict? Any suggestions or guidance would be greatly appreciated. Best regards, Rasool

Hi,I am testing the ECC on DTCM on the STM32H7A3ZI.  At start of day I initialize all of DTCM apart from a single test location.  I have a test which reads from that uninitialized location and successfully provokes the SRAM ECC interrupt, correctly reporting the address for the uninitialized location.  (I am following application note AN5342).However, I am finding that the same ECC error is raised in other circumstances, when I am confident that my code is not reading the test location.  This happens when the IDE is not connected, so it is not the IDE which is reading that location.I have another test that provokes flash ECC errors, and it is currently the code of this test that somehow provokes the SRAM ECC error as well as the flash ECC error.  However I don't think this code is reading the uninitialized location (and I have also seen other code provoke the problem).  The address reported in the FAR register is always that of my uninitialized test locati

IssueHigher ambient temperatures cause communication malfunctions with XSPI memories.DetailsOur design is heavily adopted from STM32H7S78-DK which also has the same issue described below.The application uses memory-mapped mode for both Flash and RAM as the main operational units. These memories are configured in the bootloader and everything generated using CubeMX. According to the datasheets, all three components (CPU, Flash, and RAM) are specified to operate reliably under the given conditions, and they do function correctly under normal temperatures.The problem arises when the ambient temperature increases from 25°C to 60°C. These temperatures are within the acceptable operating range for all components, as stated in their specifications. Upon reaching higher temperatures, the memories start to exhibit failures. However, further investigation revealed that the issue is not with the memories themselves. When the memories alone are heated, they continue to operate reliably, even at el

Hi,I'd like to know if execution jumps to the interrupt handler of Timer x only when the CCxIF flag changes state from 0 to 1. What happens if the flag is already set and an event occurs that would have caused the flag to switch from 0 to 1 had the flag been in the 0 state? Would the ISR be called or would it be ignored?I'm using the STM32G473VCH3 controller. Thank you.

In the documentation on STM32N657X0, it says that the memory must be connected with match length track on the boards.It says:Match length (including BGA package length)- DQS0 with IO0..7 (Byte0), all in 50 mils,- DQS1 with IO8..15 (Byte1), all in 50 mils,- CLK is100 mils from any signal of Byte0 or Byte1- NCS can be CLK +/-700 milsBut I can't find any documentation on "BGA package length".It seems reasonable that the BGA package should be taken into account, since it is 12.8 mm.and a precision of 1.27mm (50 mils) is specified.I hope someone can help me find that documentation.Keld

Hello,We have been using CANbus as our form of communication for a system with multiple nodes. Each node was individually tested with CAN and all of them work without issue. However, when we started system integration testing, we noticed significant noise on the CANbus channel that caused data to stop. To give more details, we are running 2 battery packs, a power electronics DC/AC converters (to create a 120Vac signal) and a central supervisory controller, which are all using STM32 MCUs to communicate to each other via CANbus. We are using an STM32H7AGI6, STM32F401RE, STM32F303RE. When we send a CANbus command to start the DC/AC converter, that is when the noise appears and we cannot communicate with the MCUs until the DC/AC converter is turned off. We have termination resistors at the end of the bus and I have verified that the 60 Ohm resistance is seen on the bus. I've also attached a copy of our schematic for the CANbus, which all of the nodes use (except that the 120 Ohm

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