STM32 MCUs Products

Hello everyone,I and my collegue have more than 20 years experience on embedded desing with MCUs. We have a problem which we haven't seen this kind of problem before. I guess someone can help us in here.MCU: STM32F756IDE: Project created from cubeMX and toughgfx, coded from IARThe main problem is our code jumps unknown address. We have custom bootloader, it runs first and jumps application. After it jumps user application, we initialize every peripherals again. We start freeRTOS kernel and toughgfx task. Actually the code runs well but, sometimes it couldn't run after user application starts.When we dig on it, we saw the code try to jump unknown address which is not on address space. (We get Hard fault or Bus fault or Mem Fault exeption)Anyway, we decided to remove bootloader and try to user code alone. At that moment the code started to do same thing at same location.The code star

This is a question about Receive Only Master (SPI_DIRECTION_2LINES_RXONLY).I was able to output the waveform shown in the attachment using Receive Only Master.However, no data is being received(tmp). Why is this? The process is performed in the following order:HAL_SPI_Receive_IT(&hspi2, tmp, data_size);HAL_SPI_Transmit(&hspi4, g_rx_temp_register, data_size, 1000);hspi2(Receive Only Master)hspi4(Transmit Only Slave) About the waveform in the attached image1ch hspi2 clock2ch hspi2 MISO

The reference manual 0433 Rev 8, p. 900, section 23.5.5 says "This bitfield has no effect when in memory-mapped mode (FMODE = 10)." But p. 901, section 23.5.6 says: "11: Memory-mapped mode".Could someone please let the authors fix this?Thank you.

Hello,I have an ISR for TIM4 running on an STM32F2 microcontroller. The ISR triggers on a rising edge of the timer input channel, and its purpose is to record the microsecond timestamp of the last two rising edges in global variables for other parts of the firmware to use.void TIM4_IRQHandler(void){second_last_re_us = last_re_us;last_re_us = time_us();TIM4->SR = 0;}I notice that the ISR as written triggers twice on each rising edge. This is evident by last_re_us and second_last_re_us reading

Hi,I'm using STM32G474 to drive my BLDC motor, i want to trig low-side phase current sensing ADC when the lower MOSFET is conducted. But the wired thing is even though CMP2 callback did be called by interrupt, ADC also not triggered (ConvCpltCallback not being called).I'm not using CubeMX, so i guess is there some configuration is impossible for the hardware, but i checked it in datasheet, all things should be ok for G474.ADC configuation: __HAL_RCC_ADC12_CLK_ENABLE(); this->adc1_handle.Instance = ADC1; this->adc1_handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; this->adc1_handle.Init.Resolution = ADC_RESOLUTION_12B; this->adc1_handle.Init.DataAlign = ADC_DATAALIGN_RIGHT; this->adc1_handle.Init.GainCompensation = 0; this->adc1_handle.Init.ScanConvMode = ADC_SCAN_DISABLE; this->adc1_handle.Init.EOCSelection = ADC_EOC_SINGLE_CONV; this->adc1_handle.Init.LowPowerAutoWait =

Hi Foued,I'm going to connect 10 BMI323 IMUs to STM32H503RB MCU by I3C bus. BEI323 supports I3C and dynamic addressing and 0x68 static address. Is it possible for I3C bus of STM32 to recognize all IMUs by assign different I3C addresses to make all of them working? Thanks! Yx

Hi AllI have created a PCB where I want to use the OCTOSPI to communicate with a FPGA.I have difficulty finding accurate information on how the different memory types work. I already have a Hyperram running so I started there, that did also seem straight forward.I do currently only have FPGA code listening and is focusing on getting write to work.I slowed down the clk quite a bit to only fucus on functionality. Pre scale of 30 ~9.6MhzI would much like to have the FPGA memory mapped, so that's what I'm testing.When I write to address 0x91234568 (0x90000000) is octospi1 basewith the data of 0x87654321 then i get following sequence in hex:20 12 34 56 00 04 43 21 87 65The Data is easy, that's just different order 43 21 87 65 instead of 87 65 43 21The 20 seems to be CMD

Regarding the problem that CTSIZE becomes 0x01 after SPI communication is completed,In our program, SPI-SR-CTSIZE becomes 0x01 after SPI communication is completed.In that state, if we try to perform the next SPI communication, a timeout error occurs in the middle of the communication.When SPI-SR-CTSIZE = 0, no timeout error occurs.Is there any way to set SPI-SR-CTSIZE (= TSIZE number of frames in a session) to 0?Translated with DeepL.com (free version)

[This is a reconstruction of a thread I've started on Mar 26, 2017, but got lost in the two forum software transitions since then.]Reports in IWDG short period (125 us) problem  and STM32F407 : IWDG and erase flash sector  indicate that the IWDG does not work as it's (quite simplistically) described in the RM.To find out the real working of IWDG, I took a DISCO-F4, wrote a snippet which brought out LSI through its connection to TIM5_CH4 onto a pin, wired up a LA and started experimenting.The following is my interpretation of what I've seen; I don't know what's the real implementation of course so I might have misinterpreted things. I haven't experimented with the debug facility. I

Dear all,   I'm using stm32f412ret6 MCU in my custom made board. The code used is as below. The HAL_CAN_Start function returns HAL_ERROR. when debugged the issue is timeout with in the HAL_CAN_Start function. I don't understand if I'm going wrong any where with the code. Kindly help me out with this problem. /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.c * @brief : Main program body ****************************************************************************** * @attention * * Copyright (c) 2022 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER C

I am using an STM32G473MEY3 MCU. I am looking in the reference manual in the FLASH section, but I am not sure if this is a cateogry 2, cateogry 3, or category 4 device. I am thinking category 3. Any ideas?

I am trying to use the LSI as the clock source on the STM32 G0B1KEU6. It doesn't work, and as soon as I select the LSI in the MUX on the clock tree, my code stops working. To ensure there are no other sources of error, I used the exact same code but with the HSI selected for SYSCLK. Below are the main source files generated by Cube IDE for when LSI is selected and for when HSI is selected (I attached files to this ticket). I also ran a diff to provide more detailed insights and help pinpoint the issue.

Hello, I am attempting to have a two stm32 nucleo boards communicate by sending and receiving can messages.  My goal is to have the PA5 LED of the STM32 f446re blink when a can message is received. I know that the canbus must be configured to classical can which the baud rate must match both boards. The two boards I am using are the stm32 f446re and the stm32 h723zg. Currently, I suspect an electrical issue as I have been running a two 220 ohm resistors in parallel with the CAN_H and CAN_L lines, but when in a recessive state the CANH and CANL both read 2.2V and fail to change when in the dominant state. However, I want to ensure that the software is also not the issue. I am also using two waveshare SN65HVD230 can transceivers as well. Any help is appreciated, and I have attached a picture of the set up (ignore the 7 segment) as well as each project's codebase. 

Hi,in a setup on STM32H725 where TIM1 ETR triggers several DMA activities, I observe an effect while debugging that I would rather like to avoid:Looking at the NDTR of the three DMA, it seems that one extra ADC run (or at least the related DMA transfers) occurs each time the device is halted for debugging. I do not understand how this can happen.Basic setup: TIM1 is started by ETR. Two DMA channels capture related register values to circular buffers and are triggered by TIM1 TRG and TIM1 CC4 (at CCR4=1). Combined ADC1+2 is triggered by TIM1 CC3 (at CCR3=89). The ADC results (2x 3x 16 bit) are written to a circular buffer via DMA. All DMA are initialized at the same time. The circular buffers are all of the same size.All timers are halted during debugging (flags set in DBGMCU->APBxFZ1)Observation: Normally (without any halt introduced debugger via SWD) the three DMA are perfectly in sync and stay in sync. For example, at each DMA Complete of the

Hello everyone,I'm currently using the STM32F401CCU6 in my project, but it's proving to be oversized for my application, both in terms of physical package and power requirements. I'm hoping to switch to a smaller STM32 microcontroller that maintains as much compatibility as possible with the F4 series, so I can avoid major changes to my implementation.Here are my main requirements:12-Pin Package (a few more pins are okay, but aiming for a minimal footprint)RTC Support with a 32.768 kHz external oscillatorSPI Communication capabilitiesLow-Power Modes (ideally STOP, STANDBY, or similar ultra-low power options) Any recommendations for STM32 microcontrollers that meet these criteria? I’d love to hear about your experiences with similar switches, too!Thank you in advance! 

Hi all,I am trying to activate SDADC on my custom designed board to measure a couple of analog voltages. I am trying to measure 5-channels in injected continuous mode. Offset = 0, Gain = 1, Single-Ended Offset Mode. See the CUBE settings below :In the code, I initiate the conversion by the following :  void SDADC_Start_Conversion (void) { if (HAL_SDADC_InjectedStart_IT(&hsdadc1) != HAL_OK) { /* An error occurs during the configuration of the injected conversion in interrupt mode */ Error_Handler(); } }

Hello!This is the first time im using NOR Flash so bear with me :)Question #1I screwed up and forgot to add a pullup for the open drain ready/busy NOR output.So i've tried the ghetto approach of using the internal pullup of the STM32 as "busy wait" but it sort of doesn't work. The code will wait/trigger while the NOR-Flash is busy and release once its done, as expected. However, the flash will not be programmed unless i add a "long" delay between the writes.Question #2What would the downside be to using the internal pullup and triggering a rising edge interrupt when writing a buffer to the memory?It doesn't seem possible to "automatically" write a buffer to memory or use DMA. ie that you have to write one word at a time but only send the "program command sequence" the first time if you are within the timing? Memory timingsProgram ti

Background: F429 works as a net node in the ethernet switch. Other nodes are cortex-A or CPU, so the controller with F429 has the poorest capacity for processing net data flow.Current Implementation: As the controller only exchanges data with a specific node, I use MAC filter to band the mac address of the specific node, reducing stress for driver and application..Issue: Works good for months , but data flow on the switch became much more than before, net issue occurs. It seems have 3 stage- could not communicate, communicating with delay , communicating recovery.Dose it means that the MAC core could not suffer so much data flow, and how can I solve the problem.Thank you for advises.​

How to output CLK for receive-only (master) in SPI communicationWe want to create a receive-only (master) in SPI communication.However, SPI_CLK is not generated.In the case of a transmit-only (master), I think that CLK will be generated if CLK is enabled when transmitting with HAL_SPI_TransmitReceive,but in the case of a receive-only (master), how do you output CLK?Will CLK be generated automatically if I call HAL_SPI_Receive?

Trying to write a i2c driver for the stm32f0 and having trouble understanding how this works as im use to the stm32f4 i2c could anyone describe what steps i need to take to write a polling i2c driver or point me to an app note that describes ive ben reading the reference manual and just scratching my head lol

I checked with the Uploaded File schematic board. I'm using STM32CubeProgrammer. Connect from PC via UART. I confirmed that the UART is connected with STM32CubeProgrammer. ​Software has not been written yet. In that state, the MCU became so hot that I couldn't touch it. Could you please tell me the possible reasons?

Hi I am using X-CUBE-DPOWER to set the parameters for my Buck converter operating conditions on a B-G474E-DPOW1 evaluation board. I am trying to understand how the controller is implemented. For the PWM switching frequency, I know that this is done by configuring HRTIMER.  However, I am unsure how this is implemented for the Voltage/Current control loop frequency. E.g.  If I change the value to half, which part of the MCU or code will be changed to apply this setting?Thank you.  

Hi all,I was reading through the documentation of the STM32H723 to find out what clock speed I can configure the FMC to run at using an external SDRAM. Looking at older posts and videos there is mentioned 100 MHz, but when I look at the newer/revised (revision 3) the max kernel fmc frequency has increased from 200 to 275 MHz:Does this mean that now an external SDRAM can run at 137.5 MHz (kernel clock / 2) and not 100 MHz?Best regards Links I have compared to:

I have read AN4991 and the example code but in my case nothing works. I'm using DMA transfer with the UART. Can that be the reason? Is it not possible to wake up from STOP1 when using DMA to receive bytes from USART? Or how can it be done?I use CubeMX to initialize peripherals but my "going to sleep" code is esentially like this:__HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_HSI); HAL_SuspendTick(); while(__HAL_UART_GET_FLAG(&huart1, USART_ISR_BUSY) == SET); while(__HAL_UART_GET_FLAG(&huart1, USART_ISR_REACK) == RESET); UART_WakeUpTypeDef WakeUpSelection; WakeUpSelection.WakeUpEvent = UART_WAKEUP_ON_STARTBIT; HAL_UARTEx_StopModeWakeUpSourceConfig(&huart1, WakeUpSelection); __HAL_UART_ENABLE_IT(&huart1, UART_IT_WUF); HAL_UARTEx_EnableStopMode(&huart1); HAL_PWREx_EnterSTOP1Mode(PWR_STOPENTRY_WFI);   // After USART RX start bit we should wake up from stop and continue here - but it never happens   HAL_UARTEx_DisableStopM

Hi all,My goal is to have position independent binaries for my application (on an STM32H7) so that I can update the device while running out of flash (swapping between two different program locations).I followed this tutorial: https://techblog.paalijarvi.fi/2022/01/16/portable-position-independent-code-pic-bootloader-and-firmware-for-arm-cortex-m0-and-cortex-m4/ which uses the following compiler flags -fpic, -mpic-register=r9, -msingle-pic-base, and -mno-pic-data-is-text-relativeMy application was working while interfacing with UART.  I could self update and run out of both program partitions without issue.  When I tried to swap the interface to ethernet, I was unable to boot up because of a hardfault.  Investigating further, the har