STM32 MCUs Products

Hello,I'm using two STM32F4 nucleo boards and my goal is to transmit data unidirectionnaly from one board to another using SPI in a loop.The first board is configured as a Master and it only transmits data. And the second one is configured as a Slave and it only receives data. The data is set to "ABCD" and it does not change during the test. The data is transmited without any problem. I checked it using an oscilloscope.However, the problem is that I receive the correct data only during a certain amount of time and the data is alterd after some itteration. Here is some output of the data on my PuTTy console.  

After setting configuration registers in HAL_DMA_Start_IT, DMA fails to fire back interrupt, HAL_DMA_IRQHandler(). The TransferComplete call back routine is not called but only once after reset since HAL_DMA_IRQHandler() is called only once after initialization. Flags CC1DE and CC1IE are set after initialization and never change there after. I am trying to read a parallel ADC through GPIO using DMA with interrupt and timer input capture. I am using STM32L496ZG ucontroller and used CUBEMX to generate code.Also, I am using Timer2 with input capture mode to request DMA transfer. And using MCO to generate 2 MHz to feed to PA0 for timer2 ch1.I searched the forum and checked almost everything. I used latest  CUBEMX 6.11.1 version.Your help is greatly appreciated.ThanksHere is my initzn part;    HAL_Init(); /* Configure the system clock */ SystemClock_Config(); /

We are not using SMPS functionality of STM32H747AII MCU. Can we left VDDSMPS, VFBSMPS, VLXSMPS pins unconnected?

MCU: STM32H753VI Scenario:Requirements specify that I must use internal flash memory to store error counters for our fault management system. I was going to directly write to flash memory using the built in HAL commands, but found that most people seem to use the EEPROM Emulator (specifically the one STM provides in their example). As far as I can tell, the reason people use the EE is because it provides wear leveling, and an easier to use interface for utilizing flash memory to store variables. I would like to use the EE mainly because of the wear leveling, as that is important in our specific application. Problem:I have been able to successfully use the EE on our MCU to store our error counters. However, I sometimes encounter a hard fault, and when it happens seems to be completely random. When stepping through the code, I found that the hard fault sometimes occurs wh

Posted on June 28, 2017 at 14:27Hi all,i have two custom board with a microcontroller STM32F401CC in a 48pin package. One of these two micro is not working anymore due to a programmed option byte during a debug session. ST-link tell me this micro has a 'read out protection' set to level 1 instead level 0.I tried to restore the level 0 with ST-link utility, but it can't restore the original stete to level 0(STlink gives me the correct id and microcontroller number)So, i'm trying to restore this microcontroller with the utility Flash Loader Demonstrator, using the UART1 ( pins: boot0=HIGH, boot1=LOW) using an  usb-serial adapter with this parameter 9600-8-EVEN btu i receive always the same reply:Unrecognized device... Please, reset your device then try again.I tried to use the serial bootloader with the second board (this is 100% working) and i have always the same reply:does anyone can tell me how to solve th

Hi Friends,In STM32H7 MCU, both M7 and M4 can access shared memory, such as D3 SRAM4. I am going to use a D3 SRAM4 address as a place to share some status information between M7 and M4. If a 32bits word is defined shown as below,  can the access from both sides(M7 and M4) be guaranteed atomic?  Does it need HSEM?-----Code example:volatile uint32_t *status_ptr = (status4_7 *)0x38000000;In M4 side,  *status_ptr = 0x1234abcd;In M7 side, uint32_t status = *status4to7_ptr;I know a 32bits word access is atomic in single core STM32 MCU. Thank you in advance.   

The reference manual RM0503 rev2 has inconsistent information about the flash wait states.Table 9 in §3.3.4 shows three options: 0WS, 1WS, 2WS (and, by the way, it says that all three of them correspond to "1 CPU cycle", which seems wrong).Instead, §3.7.1 (description of the FLASH_ACR register) indicates only two options for the LATENCY[2:0] field: 000 zero wait states, 001 one wait state. Which is correct?

I have a custom board with a STMWB55 (master) and a STM32F031 (slave). They communicate over SPI using DMA. Unforturenately there are communication problems.   In order to identify the problem I have simplified the setup. I have used a ST NUCLEO-F031K6 and a ST NUCLEO-WB55 board to test the communication (SCLK, MISO & MOSI are used, 250kHz clk freq). Both use SPI example provided from ST (from STM32Cube_FW_F0_V1.11.5 and STM32Cube_FW_WB_V1.19.0). The slave is setup to use interrupt instead of DMA to get the simplest setup. The only modification made from the original example is that the Master sends 8x bytes messages and the slave echoes what it receives - in order to test the slave device. Approximately 200 bits out of 10kB from the slave are errorprone. The communication is monitored using a logic analyser and the data is analysed with python.   Is this success/failure rate expected? Is this something that you

I am using STM32G474VET3 controller.As i am using DAC out voltage for my application.So i want to know the  DAC output stability, performance over temperature, & the temperature drift at Maximum junction temperature 150 °C.Also any other factors affecting my DAC out.Also how to mitigate this deviation in DAC out reading at normal room temperature to Max highest ambient temperature ambient temperature 150 deg C 

This question is about HAL_SPI_TransmitReceive.If a slave starts sending 8 bytes of data after the 4th byte sent by the master, is it possible to use HAL_SPI_TransmitReceive without a dummy (ignore) buffer?We will be the master side.Our assumption is that a dummy (ignore) buffer will be created.HAL_SPI_TransmitReceive(&hspi1, sbuf, rbuf, 12, 1000)sbuf[12] = { A, B, C, D, Dummy, Dummy, Dummy, Dummy, Dummy, Dummy, Dummy }rbuf[12] = { Dummy, Dummy, Dummy, Dummy, A, B, C, D, E, F, G, H }Is this perception wrong?

Hi,I use STM32U575.The STM32U575 works as a USB CDC ACM device and I implemented it in standalone mode.OTG_FS_IRQHandler is called when data is received from the host device.Is there a way to determine that when OTG_FS_IRQHandler is called, it is due to data reception ?Best regards.

Posted on July 28, 2016 at 07:53Hi,We are developing a display using STM32F439NIH6 Microcontroller in our design.  We have the following technical queries:We have referred to your evaluation board design and we are interfacing STM32F439NIH6 with SDRAM, NVRAM and ARINC 429 devices through FMC data bus and Address bus. Can we connect all 3 loads and access simultaneously.We are unable to drive all the three loads. During the process of analysis we came across I/O Cell Compensation in Reference Manual. Is this can be enabled for FMC?We are working on 3.3V supply and configured the System Clock as 180MHz.We tried to enable I/O cell compensation by reducing the System Clock to 100 MHz/90 MHz and 50 MHz. We are unable to enable the Cell Compensation. Please help us in this regard by providing the procedure to enable the same.

Hi there! I was hoping that the H5 series would be like a faster U5 series but instead they seem to be very cut down in terms of features. i.e. the H5 looks like a faster crippled U5.The U5 has graphics accelleration and HS USB but the H5 has neither. Will there be a H5 line that's like a faster U5 at some point in the future? What was the intended market sector for the U5 and H5 models? As a customer it seems confusing. Thanks.

* In the reference manual RM0503 rev2, in §5.4.4 (description of RCC_PLLCFGR), the description of PLLR[2:0] indicates:Caution: The software must set this bitfield so as not to exceed 54 MHz on this clock.* In the reference manual RM0503 rev2, in §5.2.9, table 32, the maximum PLLRCLK for "Range 1" is indicated as 56MHz.* In the datasheet DS14548 rev2, in Table 56, fPLL_R_OUT is indicated as min 12MHz, max 64MHz (for range 1), and as min 12MHz, max 16MHz (for range 2)* STM32CubeMX imposes a limit of 56MHz for the PLLR output (it's unclear which voltage range is used -- is it calculated or configured?)Similar issues exist for the limits regarding PLLP, PLLQ, PLLN (especially in the RM). The RM, datasheet, and/or CubeMX should be corrected so that they are all consistent. Also, the lower limits (and the fact that the limits depend on the voltage range) should be mentioned in the RM too.

Hi all,i am using STM32C011F4U6 and i want communication between Uart1 _baud rate -115200 _8N1 and Uart2_Baud rate _4800_7E1.But STM32C0 haven't 7 bit communication option. How can i do this?Thank you

I'm designing a unipolar sine wave inverter using a lookup table to generate PWM signals, but I'm encountering some issues and have a few questions:Should the values in the lookup table start from zero, or from the peak value of the sine wave?Is it sufficient to create the lookup table for only half of the sine wave cycle (0 to 180 degrees)? After generating the first half-cycle, can I simply change the polarity to complete the full cycle, or is there another method I should follow?How should I handle the transition between the first and second half-cycles? Should I invert the polarity of the PWM signal, or do I need to modify the lookup table values?Could someone provide a small example of a lookup table for a unipolar sine wave inverter, and explain how to use it across a full cycle?I'm able to generate a sine wave without using complementary channels, but when I try to use complementary outputs on two channels, it doesn't work corre

Hello I'm currently trying to change the classic CAN into FDCAN, but when i try to change the clock source of FDCAN (which is PLL1Q) from 50Mhz to 80Mhz to use FDCAN, the clock configuration keeps giving the message "wrong parameter values" when i try to generate it.In the datasheet of stm32h753VIT6, it says "The clock calibration on CAN unit is designed to operate under the following conditions:• a CAN kernel clock frequency fdcan_ker_ck up of at least 80 MHz"which means the clock of FDCAN must be setted to at least 80MHz, so the clock must be setted to 80MHz in order to use FDCAN.At this clock setting, the only thing that uses the PLL1Q setting is FDCAN, so why can't I use values above 50MHz? I'll attach the ioc file that is associated with this issue. 

I am using the DMA to transfer data from UART 1 (Channel 2) and UART 2 (Channel 4). Every once and awhile the data seen on UART 2 which has a lower DMA priority will be "corrupted" by the UART 1 data. I know this because when I disable UART 1 routines, UART 2 receives perfectly everytime. This is never an issue with transmission on UART 2 even when UART 1 is enabled.This is on the STM32F072CBU6 MCU. Both DMA protocols are initialized identically for UART 1 and UART 2.I will post most of the code related to these functions.Any ideas would be greatly appreciated! UART initializations:uint32_t Tmp; huart1.Instance = USART1; STM32_GPIO_Init(RS485_TXD_GPIO_Port, RS485_TXD_Pin, GPIO_MODE_AF_PP, GPIO_PULLUP, GPIO_SPEED_FREQ_HIGH, GPIO_AF1_USART1, 0); STM32_GPIO_Init(RS485_RXD_GPIO_Port, RS485_RXD_Pin, GPIO_MODE_AF_PP, GPIO_PULLUP, GPIO_SPEED_FREQ_HIGH, GPIO_AF1_USART1, 0); hdma_usart1_tx.Instance =

I have a custom board that I need update by USB. I have a jumper that allows setting the following:nboot bit set to 1BOOT_0 pin set to 1. Then I power on the board and I can see the stm32 bootloader device on my windows machine. First I get a similar behaviour as https://community.st.com/t5/stm32cubeprogrammer-mcus/problem-with-dfu-and-stm32f072b-discovery-board-cubeprogrammer/td-p/254296 . However, after accepting the disable request from the STMCUbeProgrammer (even though it was never enabled) i get the error (Device is under Read Out Protection)

 /* USER CODE BEGIN Header */ /** ****************************************************************************** * @file : main.c * @brief : Main program body ****************************************************************************** * @attention * * Copyright (c) 2024 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ /* Private typedef ------------------------------------

stm32g474ve , dma can be triggered using external interrupts, but dma cannot be triggered using software.  In theory, both external interrupts and software interrupts should trigger events. At the same time, I have verified that stm32h750 is OK. So I want to know what I didn't think about.  

Hi, I am new to ST, trying CAN TX RX Code. Every time I Transmit Error frame is getting generated instead of Data . Please  suggest what i am doing wrong in the below code.  I am sharing my main file   Thanks

libusb: info [darwin_claim_interface] no interface found; setting configuration: 1 Device : MACBOOK AIR STMicroelectronics ST-LINK GDB server. Version 7.5.0Copyright (c) 2023, STMicroelectronics. All rights reserved. Starting server with the following options:Persistent Mode : DisabledLogging Level : 1Listen Port Number : 61234Status Refresh Delay : 15sVerbose Mode : DisabledSWD Debug : EnabledInitWhile : Enabled libusb: error [darwin_claim_interface] could not set configurationDevice connect error Error in initializing ST-LINK device.Reason: Failed to connect to device. Please check power and cabling to target.

Hello everyone,  I am trying to generate sine wave using DAC and interrupts in my STM32F446 board. I want to do it without using array model. I am getting b infinite_loop when the program is run in debug mode. I have initialised "use float with printf/scanf" settings. The code is as follows:- #include "stm32f4xx.h" #include <math.h> volatile float data; #include "dac_sine.h" #define pi 3.14159265359 volatile uint32_t theta = 0; volatile uint32_t del_theta = 1; float value; void dac_sine_gpio_init(void) { RCC->AHB1ENR |= (1U<<0); //enable clock for GPIO Port A GPIOA->MODER |= (0b11<<10); //setting PA5 in analog mode GPIOA->MODER |= (0b11<<8); //setting PA4 in analog mode } void dac_sine_timer_init(void) { RCC->APB1ENR |= (1U<<29); //Clock access to DAC Enabled RCC->APB1ENR |= (1U<<0); //clock access to Timer2 Enabled

I'm planning to drop in an STM32L083RC into a design made for STM32L071/073/083RZ (LQFP64) and was confident after reading AN6091 that apart from USBVDD it would be pincompatible.It appears I cheered too soon, after I dived into the U083 datasheet and pin functions: The STM32U0 misses the second MCO output on PB13(pin 34) and the USART on PB3-PB4 (pins 55-56), where the L07x has USART5.That results in quite a bit more redesigning than only disconnecting the unused USB power.I guess that the AN6091 document should warn in Table 21 that USART pinout compatibility is partial and in Table 25 that the second MCO output of the L07x is not available on U0 series.