STM32 MCUs Products

Hello,I had a problem with Nucleo H723ZG ADC, i needed ADC error to be less than 1mV and a sampling rate of 2.5MSPS, but the built-in ADC was having errors around 20mV. (topic).So i decided to proceed with an External ADC, ADS9219 The problem with this one is that the interface for this ADC is Serial LVDS, when i looked it up

Hi，There is a STM32F407 on my board to configure and control the optical module. Also, STM32F407 use SPI to interface with CPU. STM32F407 work as SPI slave mode, and CPU work as master mode. Some protocol require one flow control byte in SPI timing, such as OIF protocol. My understanding is :For read operation. After slave receive the operation code and address, slave need time to prepare data according to address then put the data into TX_Buffer. This all will be finished in the one clock period as below red mark shown. If slave can't finish the job in time, slave must inform to host through flow control byte .

Hello all, I have been struggling with DMA transfers from SPI transactions and would love a second opinion on what I could be doing wrong. I have confirmed that polling works and I can corroborate the data I see in the RX registers with a scope. I do not use the HAL API for SPI receptions with DMA, I am mostly using low-level register modifications to trigger read/writes from the SPI peripheral, although I do use the initialization of the peripheral that is generated by Cube IDE.I was looking into why the DMA destination buffer was not being filled, when I realized there was something wrong with the SPI transaction itself. According to the RM, the DMA will make a request once RXP is set and it is automatically activated according to `RXWNE` and `RXPLVL`. When inspecting these register during the transaction I see that `RXWNE` is set to 1, meaning there is, at least, 4 bytes in the RX FIFO. RXPLVL itself reads all zeroes since the data size is larger th

Hello,I am having trouble memory mapping both OSPI ports at the same time. Can I run a QSPI Flash on OSPI1 and a OSPI Hyperbus RAM on OSPI2 and have both be memory mapped or do both OSPI ports need to be running in the same mode to be memory mapped?Thanks,Dan

I am evaluating the STM32H743VIT6 microcontroller for my project. I would like to know whether this device supports Execute-In-Place (XIP) from external flash memory through QSPI

Hi everyone, i just want to be sure cause it's the first time playing with the bootloader.I have a STM32C092 (TSSOP20) an i was wondering if i can flash it through FDCAN, but reading the AN2606 i unfortunately found a postilla as following (page71):Flashing through can with a TSSOP20 isn't possible, after a second look even the datasheet said the same thing.So there are any other method to flash through FDCAN?My only option seems to be boot from RAM and writing my own bootloader into the application, it's that correct? Thanks,Sander 

Hi STWe saw from STM32F302x6/x8 device errata ES0247 - Rev 8 - February 20192.4.4 ADEN bit cannot be set immediately after the ADC calibration is done Description At the end of the ADC calibration, there is an internal reset of ADEN bit 4 ADC clock cycle after the ADCAL bit cleared by hardware. Due to that, if ADEN bit is set within those four ADC clock cycles, it will be reset by the calibration logic and the ADC will stay disabled.Workaround Adopt one of the following measures:Continue to set the ADEN bit, until ADRDY bit become '1'.After ADCAL is cleared, wait for a minimum of four ADC clock cycles before setting the ADEN bit. The workaround 1 seems conflict with RM (RM0365 Rev 8):Software is allowed to set ADEN only when all bits of ADCx_CR registers are 0 (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0

I'm using ADC with DMA in a large project, and faced some very strange problem: If I'm using DMA2 Channel 6 - ADC works correctly If I'm using DMA2 Channel 1 - the SW end up in Hard Fault 

Heyho,still checking L1 for new project, next question:Are the L1's internal EEPROM register interface, erase, read, and write functions the same as on L0 (we're already using that) ?Obrigado!

I am using STM32F401, I had an application which communicates via USART1 by using DMA2. Both RX and TX DMAs are working fine. So I added a bootloader and moved application to 0x08008100. Bootloader is using same USART1 and DMA2. Now bootloader is working fine but I have problem with application.All I changed in application is start address. Bootloader jumps to application, timer interrupt is working fine and toggles LED. When it receives or transmits a data via DMA it stops, LED is not toggling anymore. When debugging I tried these:* SCB->VTOR is already set as 0x08008100. Timer interrupt is working fine.* I changed application's start address back to 0x08000000 and its working fine. * I removed USART and DMA code from bootloader so it only jumps to application. It didn't solve the problem (it lloks like not deinitialize-initialize issue).* I added USART and DMA to bootloader back. In the application I didn't use DMA when sending data

Hello everyone,I'm working on an In-Application Programming (IAP) solution for an STM32F303CC. I've divided the flash memory into two application areas (let's call them App1 and App2), and I want to rewrite the program in App2 from code running in App1.I have already implemented this, and it seems to be working correctly. However, I have some doubts and would appreciate it if anyone with knowledge on this topic could provide some clarification.Here is my implementation detail:The code that erases the App2 area is located in the App1 area.It executes the standard HAL sequence: HAL_FLASH_Unlock(), HAL_FLASHEx_Erase(), and HAL_FLASH_Lock().Global interrupts are not disabled during this process.Several interrupts are active, but I have confirmed that all of their ISRs are also located within the App1 memory area.My under

I am using STM32f756 Nucleo board. I have an rgb lcd interfaced via 18 bit (rgb666) connection with the mcu. I have previously used pixel format L8 with CLUT and successfully produced output on the display. Now, I have changed the pixel format to rgb565, changed the frame buffer to 16 bit and populated it with rgb565 values for each pixels. But there is no output on the display unless I enable the CLUT again. I understand that CLUT is only useful for 8bpp. I don't understand why in RGB565 pixel format, the display doesn't show anything without enabling CLUT.My setup is as follows -

Hello ,I am working on a project using the STM32G431KBT3 MCU with STM32CubeIDE. My setup includes:ADC1 configured to read 3 channels (CH2, CH3, CH4) in polling mode.TIM2 configured in PWM input mode to measure the frequency and duty cycle of an external PWM signal on CH1.The program runs as expected initially, but when I run the program again, I notice in the Live Expressions window that the values of variables appear to interchange:adc_val_ch1 appears to show the duty cycle value.duty_c shows adc_val_ch1 channel values.Similar behavior is observed for other ADC variables. when ADC and TIM2 interrupts run simultaneously the values are interchange, for reafference here I attach my code as w

Hi, I started working on my own dev board for a flight computer based on the STM32H747BIT6.At first, I struggled a bit to connect the board to the computer, only managing to do so using the hot plug mode in order to get some info from the microcontroller. My problem comes when trying to write something to the flash: it gets stuck on erasing internal memory sector 0. This means it is unable to write or modify the flash memory. Also, when I connect the board to the STM32CubeProgrammer, it shows me the flash memory, but every address is at 0, which makes sense given that I haven’t uploaded any code to the microcontroller.I’m not really sure what this means — I’m able to read it, but not write to it.The thing is, I started measuring the power source pins just in case I spotted something weird, and I sure did: my VCAP pins are at 2.2V, which is strange because they should be at 1.2V according to the internal

I am having issues with Ethernet+LwIP+FreeRTOS on the NUCLEO-H7S3L8.  I was able to get Ethernet+LwIP to work on baremetal, but adding the RTOS and threading is having issues. I have attempted to follow the process here, but am still having issues.  I pulled the reference projects here, and attempted to merge the `ETH_CODE` code blocks over.  Still, the NUCLEO-H7S3L8 doesn't respond to my pings.  However, I am able to run the reference projects on a NUCLEO-H753 without an issue.  Note that I have disabled the MPU and Data cache for the time being.My IOC and STM32CubeIDE project are attached.  Does anyone have similar issues with the latest CubeMX/CubeIDE?

MCU：STM32G070CBTx LQFP48My question is as follows: Why is it necessary to execute HAL_ADCEx_Calibration_Start() to calibrate EO and EG before using the ADC?Why isn’t this calibration performed at the factory before shipment?

Hi,I am facing issue with bootup in stm32h745xih6 controller. I am able to initiate debug for CM7 but when I initiate the same for CM4, in that case CM 4 does not go in debug and it fails and following error in there:<terminated>MOSv1.2_CM4 Debug [STM32 C/C++ Application]<terminated, exit value: 0>arm-none-eabi-gdb (14.2.90.20240526) <terminated, exit value: 18>ST-LINK (ST-LINK GDB server) Whereas same application runs perfectly fine on STM32h745i discovery board.So what could the issue be, could it be SW related or HW is at fault only?

I bought the STM32H750B Discovery and wanted to program a first example "LTDC Paint" on the demo to start. I am using the STM32Cube IDE version 1.9 (default installation, no changes made).Procedure:- File -> New -> STM32 Project -> Examples -> select the Discovery Board -> select the LTDC Paint example -> Run LTDC Paint  Then I get the following error message, see attachment:"Failed to execute MI command.... Load failed ... LTDC_Paint.elf" Which configuration did I miss?

My understanding is that when setting BFB2, Bank 2 is remapped to 0x0800 0000.Why should we need to set VTOR on reset if thanks to remapping it should interact the same?Meaning I expect the start of my vector table for app2 to be at the same address as app1 since I have not modified it.I had to uncomment #define USER_VECT_TAB_ADDRESS so that SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;would run during the SystemInit function at reset.For context I am compiling two programs with little difference in code and with the same linker script. /*!< Uncomment the following line if you need to relocate the vector table anywhere in Flash or Sram, else the vector table is kept at the automatic remap of boot address selected */ #define USER_VECT_TAB_ADDRESS #if defined(USER_VECT_TAB_ADDRESS) /*!< Uncomment

Hi, Please help me sort this out.I am trying to port a custom bootloader originally written for the SAMD21 Arm chip to the STM32U385VGT6. We are upgrading our current product with an STM32 Chip. I am having problems with switching from the bootloader to the application binary. My bootloader is loaded at address 0x08000000. The application binary is compiled to run from 0x08010000. I edited the linker script files to locate the binaries properly and tested opening the binary file with a hex editor. All seems situated correctly. Here is my function to jump to the application. APP_CODE_START is set to 0x08010000. I get "jumping to application" in my debug terminal. But the application code is not running.  void jumpToApplication(){    DEV_DEBUG_LOG("jumping to application");

After configuring SPI1 in CubeMX and calling HAL_SPI_Transmit, I get a signal on the SPI1_MOSI line, but no signal on the SPI1_CK. I have confirmed that the pin is working correctly with other code and tried different clock speeds to see if that was the problem. Any ideas on why a clock signal is not being sent over SPI1_CK?

When we were working on a small batch, we encountered a situation where one of about 100 pcbs would frequently trigger a hardfault. We found that the problem would recur when the cache was enabled. When the mpu was enabled and configured correctly, it would run normally. Only this one MCU had this problem. We determined that this was an individual, low-probability problem. Through experiments, we felt that the default memory attribute of its peripherals was normal, not device, which caused the error when accessing a reserved address during cache.

Heyho,just checking the L162 for a new project, then found that the ADC can only be clocked by the HSI.Is that correct?If yes, why?My experience with HSI (and other RC-oscillators) is that it is "mediocre" at best, rather inaccurate and jitters like crazy. Although this might not be a big issue with a 12-bit ADC.Merci!

Hello Community For some reason, my post from yesterday did not go through and was marked as spam. I'm not interested in moaning about it right now, as I have managed to brick my custom board, designed with STM32H743XI and would be more interested in finding a way to unbrick it. Before jumping to any conclusion, please read the post as it contains crucial info and things I have already tried, which you would like to suggest. Some info about my setup, as mentioned earlier, it's a custom board with BOOT0 and RESET pins exposed using a switch, and there is a JTAG interface for debugging purposes, along with a SEGGER JLink. The way I managed to brick is that I accidentally pulled the RESET line while flashing a FW using Jlink, and since then, it seems memory is in locked mode, and neither Jlink nor ST-vLink is helpful in the rescue mission. Things I have already tried and did not work... maybe I am missing something. I have been in this situation

I am using STM32H723 and have implemented WWDG. Below is my configuration:  Are there possibility that when the system resets due to watchdog it would not trigger its ISR.