STM32 MCUs Products

Hello,I originally tagged onto this thread: https://community.st.com/t5/stm32-mcus-products/stm32f103-hse-crystal-capacitors/td-p/771200 but I was recommended to make a separate thread. Many of the STM32 datasheets, such as the STM32H753, say that the pin capacitance is 5pF per pin. When trying to size a crystal for the HSE oscillator, the designer is told to follow AN2867. When trying to calculate the stray capacitance we (at a minimum) add the pin capacitance of the two oscillator pins to get 10pF. The STM32H753 datasheet even says to approximate 10pF here on page 232:

Hello Which are the correct Capacitors to use for HSE on STM32F103 with the following Crystal?Frequency: 8 MHzLoad capacitance CL: 20 pF Thank you in advance for a quick hint.RegardsMichael 

Posted on July 10, 2018 at 14:37I've been designing sub-gram boards for data logging on songbirds using the stm32l432.  Although mostly I use ultra-low power external RTCs, I recently built a test board using a 4pf 32768 crystal.  The question was then how to determine the load capacitors.  After reading the relevant ST appnote and stm32l432 datasheet I assumed that the pin capacitance was ~5pf and, given the simple board, minimal stray capacitance.  This suggested 3pf load capacitors((4-5/2)*2) and a load error of 1.5pf without capacitors.   With a predicted error of 125ppm/pf, I thought it reasonable to try without any additional capacitors in the hopes of saving board real estate in the final design.  I did include capacitor footprints for my test board.   Upon testing, I found an error > 800ppm which was surprising for two reasons -- it suggested a much larger load error than 1.5pf and also made clear t

Hello, I'm using an STM32H750VB and am trying to use the HSE crystal to communicate over USB to my computer, but it isn't able to connect to my computer. I suspect that the issue lies with the crystal since I tried to probe it with an oscilloscope and wasn't able to get any sort of reading. Additionally, when I run a timed LED blinking code using the internal oscillator, it works properly, but when using HSE it doesn't blink. I attempted to calculate the values of the capacitors based on the crystal load capacitance of 8pF. Based on the image of the circuit and crystal parameters does it look like there is an issue with compatibility or component values? 

Hi,I have developed custom board with STM32C071CBT6. I configured USB port with USBX in CDC mode. I configured USB device descriptor values as below: When I connect host Windows 11 PC to my custom board, device manager on PC shows - USB Serial Device(Comxx). It does not show product string as 'STM32 Virtual ComPort'.Please help debugging this issue.Thanks,Pradeep

The STM32L052K8u Bootloader is replying to my GoToAddress command with 0x3F. I can't find any documentation that describes reply code 0x3F.The entry in my STM32L052K8UX_FLASH.ld file says this:/* Memories definition */MEMORY{RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8KFLASH (rx) : ORIGIN = 0x8000000, LENGTH = 64K}So, I believe the correct address to send with the GoToAddress command is 0x08000000. Here are the messages exchanged between the code running on my PC and the UART of my STM32L052K8u -  which powered up in Bootloader mode because it sensed the right state of the BOOT pin. My goal is for my PC to tell the Bootloader exit Bootloader mode and jump to running my application, which is already stored in the flash. Please advise. From the PC's perspective:1.

Hi all,I'm struggling to get the ST bootloader on a STM32L431KUB to communicate with a STLINK-V3SET via CANBUS using the STM32CubeProgrammer, the reported error is ST-LINK error (BRG_CAN_ERR) Establishing connection with the device failed.I have made an adapter board with a MCP2551 transceiver which is connected via flying leads on CN9 of the STLINK-V3SET. I can connect a CANBUS analyzer to the output of this and see that the STLINK is sending messages to id 0x79, so I am confident this is working as expected.My target is a custom PCB with an 8Mhz external clock and a TCAN322 CANBUS transceiver, which functions correctly when I load my application software through the SWD interface.  I can also see that the uC is going into the bootloader when the BOOT0 pin is pulled high or the device memory is blank, by using the SWD interface and checking the program counter is in the 0x1FFFXXXX range.  However despite seeing the expected messages on

Hello Team,We are using STM32F765IIT7 MCU.We would like to get the radiated immunity document if tested (to get a understanding how good this controller is with single event effect)Kindly share any supporting documents.Best Regards,Yuvakumar

Posted on March 12, 2015 at 15:41 Here's what appears to be a another defect in the STM32F373 (See /a7981b0 /638d212). When you configure the SAR for externally triggered group conversions (the code example provided here is for regular group, but I've verified this also happens with injected groups), the group only gets triggered the first time. After that, conversions never run. If you examine the timer (trigger) and ADC registers, you'll see that they're all configured correctly, even though no conversion is occurring. Here is a minimal amount of code to replicate the issue. Processor is an STM32F373CBT6. I started from the STM32F37x DSP_StdPeriph_Lib project at Project/StdPeriph_Examples/ADC/ADC_DMA. I removed the LCD code, modified the ADC for an externally triggered regular group and added the timer initialization. If you read the description of the linked defect, you'd see that the first DMA transfer actually occurs in the timer cod

Hello I'm using trying to access to an external flash through the SPII try to send 5 bytes, my SPI transmit function work well if I put some delay (1us) between each byte, if I don't put this delay transmission start and stop just after 4bits.green -> clkyellow -> csblue Mosisame code with delay activated

Hello,probably I miss something, but  I have searched long enough so things start to get unclear.I have set up RTC on STM32U0, so I expect is to be running. But ist does not free running:<(gdb) mon sTarget voltage: 3.24VAvailable Targets:No. Att Driver1 STM32U07 M0+(gdb) att 1Attaching to program: /samsung/home/bon/devel/en_apps/caltime/stm32u083c-dk/caltime.elf, Remote target0x08004a00 in Stm32RtcV2PollSync ()at /samsung/home/bon/devel/en_apps/ethernut/nut/arch/cm3/dev/stm/stm32_rtc_v2.c:110110 while ((RTC->ICSR & RTC_ICSR_RSF) != RTC_ICSR_RSF);(gdb) p /x *RTC$1 = {TR = 0x164928, DR = 0x249024, SSR = 0xff, ICSR = 0x17, PRER = 0x7f00ff, WUTR = 0xffff,CR = 0x3000, RESERVED0 = {0x0, 0x0}, WPR = 0x0, CALR = 0x0, SHIFTR = 0x0, TSTR = 0x0,TSDR = 0x0, TSSSR = 0x0, RESERVED1 = 0x0, ALRMAR = 0x0, ALRMASSR = 0x0, ALRMBR = 0x0,ALRMBSSR = 0x0, SR = 0x0, MISR = 0x0, RESERV

I want to write a program for a fresh (first time power applied to it so there is nothing in Flash) STM32G0B1 that executes in RAM, resets the nBOOT_SEL bit in the Option Bytes (to allow DFU Mode to be invoked when Flash has been written).  The reason why I want to execute in RAM is to avoid having to run a program that is loaded in Flash (and resets nBOOT_SEL as discussed above) which is loaded into Flash that requires a power cycle to restart so that DFU Mode can be enabled in the MCU to load the actual product firmware.  This is being done in manufacturing test, so avoiding a power cycle (which takes about a minute due to other hardware in the application) would be of advantage.  Could anybody point me to:A dfu-util statement that a bin file at a specific SRAM address and has execution continue from therePointers to how the application would be configured.  What I have found so far are:

Hi,I'm using the FDCAN2 of the STM32G474VET6 for a project and I need to reshape the RAM Message memory in order to adapt it to the FDCAN Classic.Actually the configuration of the RAM Message, by default, is written for FDCAN. So I have the following configuration:#define SRAMCAN_FLS_NBR   (28U)        /* Max. Filter List Standard Number     */#define SRAMCAN_FLE_NBR   ( 8U)        /* Max. Filter List Extended Number     */#define SRAMCAN_RF0_NBR   ( 3U)        /* RX FIFO 0 Elements Number            */#define SRAMCAN_RF1_NBR   ( 3U)        /* RX FIFO 1 Elements Number      

I am trying to code the stm32h743 for spi communication and i can't seem to transmit. I am using PA5 as SCK and PD7 as MOSI. I read the procedure required that is in the reference manual (49.4.9 https://www.st.com/resource/en/reference_manual/dm00314099.pdf ) and wrote the code below but it doesn't transmit 0x3 (checked with oscilloscope).RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN; // clock enable for gpio A,B,D RCC->AHB4ENR |= RCC_AHB4ENR_GPIODEN; RCC->AHB4ENR |= RCC_AHB4ENR_GPIOBEN; RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; // enable SPI clock GPIOA->MODER &= ~GPIO_MODER_MODER5; // enable alternate functions for gpioa and d GPIOA->MODER |= GPIO_MODER_MODER5_1; // 0b10 for alternate function, (PIN5) GPIOA->AFR[0] |= (0x05 << 5 * 4); // AF5 for SPI which is 0101 (it's a 4bit variation) GPIOA->MODER &= ~GPIO_MODER_MODER6; // PIN6 GPIOA->MODER |= GPIO_MODER_MODER6_1; GPIOA->AFR[0] |= (0x05 << 6 * 4); GPIOD->MODER

Posted on November 26, 2015 at 17:56Hi,I'm experiencing a very bad behavior of HRTIM.if output set register is set on Period and output reset register is reset on CMP1.if CMP1 = 0x20, the PWM output is a narrow pulse as expected. but if the CMP1 < 0x20 the output go to active state. The duty cycle goes to near zero to 100%. This is very bad!the section 10.3.6 of the RM0364 states that:if the set and reset events are generated within same HRTIM clock period, the reset event has the highest priority and the set event is ignored. But what is happening is the opposite of it.Someone else noticed this issue before or I'm missing something?

Hi,Thanks in advance for your attention.I'm wondering if any examples are available about transmit and receive raw ethernet frames.The examples in STM32CubeH5 use the TCP/IP stack NetXDuo and transmit packets built on the upper layers of the stack and pass received packets to the upper layers.How could I transmit/receive single raw ethernet frames to handle a custom layer 2 protocol?Comparing with what is done by NetXDuo:In transmission (as in _nx_driver_hardware_packet_send) I could build the ETH_BufferTypeDef with the next pointer to NULL and send a single buffer?In reception (as in _nx_driver_hardware_packet_received) in HAL_ETH_ReadData, the HAL_ETH_RxLinkCallback must be implemented to chain all received packets from the Rx Descriptors? Is not possible to receive and process a single ethernet frame? It's confusing to me... And what is the purpose of HAL_ETH_RxA

Hi everyone, I started to work with G4 series. Everything was smooth with Nucleo 431RB board until I made a custom pcb withSTM32G473RE. Code is working very well after loading, debug also fine. but when I unplug the stlink and give the circuit a power off/on code doesn't start until I give it a reset with reset button. then it works fine. I created my projects via CubeMX I saw NRST pin is a regular GPIO and there is no configuration to set it as NRST. So I leave it in Reset State. Does anybody stumble across similar problem? or any idea what might I do wrong? Even simple led blink has same results. Any help will be most appreciated.Best regards,Zeki

Dear STMicroelectronics Team & Community,I am writing to report an apparent error in the STM32H72x/73x/74x/75x System Architecture Overview Application Note (AN4891) , specifically on page 28 , regarding the Flexible Memory Controller (FMC) section.The document states:"For STM32H72x/73x, only SDRAM bank 1 can be remapped from 0xD000 0000 to 0x6000 0000 ."However, based on the STM32H7 reference manual and other technical documentation, the default address for SDRAM Bank 1 is 0xC000 0000 , not 0xD000 0000 . Therefore, the correct remapping should be:"For STM32H72x/73x, only SDRAM bank 1 can be remapped from 0xC000 0000 to 0x6000 0000 ."This discrepancy could lead to confusion

https://rristm.github.io/tomas_materials_v2/RRISTM/stm32u5_workshop/master/5_gpdma_handson_2d_address_mx.md/3I followed this document, but the UART value is coming out as garbage. The data is being output as 8-bit, but the variable used to store it is 32-bit, so I think that's causing the issue. How can I solve this

I am trying to use SPI communication with the STM32H562 (for FPGA programming purposes).  The reference manual states that if SPI_CFG2's SSM = 1, the NSS can be toggled High/Low by switching the SSI bit in SPI_CR1.However, the switching of SSI is not reflected in the oscilloscope observations. Additionally, I tried setting the NSS port as GPIO instead of SPI communication and using HAL_WritePin to configure it, but this was also not reflected. When using the NSS port for SPI, should I set the start register bits such as SPE and CSTART?

Dear Team,As per the datasheet, the PF11 is used for BOOT0. However STM32CubeIDE doesn't specify the PF11 as BOOT Pin in the IOC File.  Also, The Reference Manual doesn't specify usage of the BOOT Pin (Grey marked area).

I have a U575VIT and am using 4 banks of touch giving 12 channels.When I use the device configuration tool to configure it calculates the number of banks used to be 9 but should be 4?It is defined in tsl_conf.h:/** Total number of channels in application (range=1..255)*/#define TSLPRM_TOTAL_CHANNELS (12)/** Total number of banks in application (range=1..255)*/#define TSLPRM_TOTAL_BANKS (9)/** Total number of "Extended" TouchKeys in application (range=0..255)*/#define TSLPRM_TOTAL_TOUCHKEYS (0)/** Total number of "Basic" TouchKeys in application (range=0..255)*/#define TSLPRM_TOTAL_TOUCHKEYS_B (12)/** Total number of "Extended" Linear and Rotary sensors in application (range=0..255)- Count also the 1-channel linear sensor used as TouchKey*/If I change the allowable limit to 9 (from 8) then it all works fine.#if ((TSLPRM_TOTAL_BANKS

 Hi,I’m working on a bootloader-based setup on STM32 where the application firmware can reside in two different flash regions:Slot 1: 0x08008400Slot 2: 0x08063400 (e.g., for OTA update)The goal is to use the exact same binary in both locations — just copy it from one slot to the other and jump to it from the bootloader.My questions are: Is it possible to run the same application binary from two different flash addresses? If yes, what needs to be done to make it work correctly (e.g., vector table, absolute addressing, stack setup)? Are there known limitations or compiler/linker-related issues that would prevent this from working safely?What I already do in the bootloader:I jump to the application slot by reading its MSP and Reset_Handler address from the vector table (fi

I tried to use STM32G0B0 DMA1-1/2 for I2C1, DMA1-3/4 for USART1, DMA1-5/6 for I2C2. Channel 1 to 5 work properly. Channel 6 (I2C2-TX) works but TC INT doesn't fire. I tried switch I2C2 -TX from channel 6 to channel 7 or to DMA2- channel1 to 7, none works. Also, I found DMA1-6/7 works without INT firing only, but DMA2 not work at all. It seems STM32G0B0 equipped with STM32G030 which has 5 channels of DMA.

Hi Team, We are using the STM32H753VIH6 in our design. We are connecting the Realtek RTL8364 through RMII interface.Connections are in the attachment and we have validated link between the two.I have captured the waveforms , but the voltage span looks incorrect(going beyond 3.3V)  because the STM is powered by 3.3V. Need inputs to capture proper waveforms. ThanksManikandan R