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Goal boot from a Quad SPI flashI shouldn't need to change any OTP settings.  Any sNor flash chip connected to XSPIM_P2 that can operated in single spi mode can be booted off from? From my understanding if we want to make a dev board and use a different external memory that is not Octo SPI flash but just Quad SPI flash we shouldn't have to change any of the OTP registers.  SinceIn sNor flash it starts in single spi modeThen in your FSB you can configure the SPI to your given device(From my understanding)There are no OTP registers for Nor flash settingsThese are all setup in the ROMChanging OTP 11 bits (5-8) would force us to loose the ability of Dev up (From my understanding) Most of this info is from theHow to proceed with boot ROM on STM32N6 MCUshttps://www.st.com/resource/en/user_manual/um3234-how-to-proceed-with-boot-rom-on-stm32n6-mcus-stmicroelectronics.pdf  No boot source is programmed in OTP default source is serial NOR No configurati

I have a STM32N6570-DK and i can't seem to program it any more.  I tried it in both the STM32 programmer gui and terminal application.  So i can connect to the device read and read the flash but i can't seem to write to it any more.  I can't even erase the flash.  I have another  Boot 0 = 0 (L)Boot 1 = 1 (H)     

i need build a slider as following picture, when i change the item up and down , at the same time, the slider need move up and down with the item's movement;    

Hello, I am working with the STM32H7B3I-EVAL board I have I2C slave model work properly the default adress used by contoller given in schematich work on 84 aand 85 adress but the other peripheral adress not get give me the roadmap for the coding of communication protocols I2C Slave Address detect. how can i code done for other peripherals using mfx expander give me solution     didnt solve the issue. Thank you  

Hi everyone,I’m working on a battery monitoring prototype using an STM32F303. I’m measuring multiple analog voltages using the internal ADC with DMA. The ADC readings fluctuate by ±20 counts whenever the PWM output for the buck converter is enabled.I already added averaging in firmware, but the noise is still visible. The analog input traces are routed near the switching MOSFET area on the PCB.My questions:Is this more likely caused by ADC sampling timing or switching noise coupling?Would increasing ADC sample time help in this case?On the PCB side, should I separate analog and power ground planes or just improve return current paths?

Dear STM expert:     Currently, Iam facing an issue:when using the stm32f030f6p6 chip, I cannot find this chip model when creating new projects in stm32cubeide and stm32cubeMX ,thus it making it impossible to new projects,what this?hope a reply..thanks.

New question split from this post. OK THANK  YOU @mƎALLEm , CAN U SHARE THE RMII CONFIGURATION FOR STM32H745BIT6?  

I've developed on an STM32U5A9J-DK using ThreadX, which, via USBX, creates a loopback audio interface between the PC and the device in the way: PC->speaker on device->microphone on device->PC.The devices are correctly seen and are working, as I'm able to enumerate them on the host and the device correctly receives audio frame,s and I'm able to process them into the device.Now, the issue is that I'm unable to send the audio packets back to the host.My implementation is pretty simple: I'm using the USBD_AUDIO_PlaybackStreamFrameDone function to read the audio frames and send them back to the microphone interface withVOID USBD_AUDIO_PlaybackStreamFrameDone(UX_DEVICE_CLASS_AUDIO_STREAM *audio_play_stream, ULONG length) { UCHAR *read_buffer; ULONG read_length; UCHAR *write_buffer; ULONG write_length; AUDIO_FRAME_MSG frame_msg; AUDIO_FRAME_BUFFER *frame_buf; /* -------------------------------------------------------------------------- */ /* STEP 1: Get A

STM32CubeMX v6.17.0While configuring an STM32CubeMX project for an STM32H753 Ethernet project on a NUCLEO-H753ZI, I observed some strange behavior.After enabling memory management, including the checkboxes- Apply Application Regions Settings to Peripherals and- Apply Application Regions Settings to Linker Files,I would have expected the memory regions to be included in the linker description file STM32H753XX_FLASH.ld.Unfortunately, this was not the case.However, since the STM32H753XX_FLASH.ld file had obviously been regenerated, I did not suspect the file handling itself.After several hours of searching, I discovered that if the .ld file is deleted before regeneration, different content is generated.Steps to reproduce this:Open STM32CubeMXFile / New Project… / Board SelectorSelect NUCLEO-H753ZIIn „Board Project Options“ dialog, click button „Unselect All“Set Project Manager / Project / Toolchain / IDE  to CMakeand Default Compiler/Linker to ST Arm ClangFile / Save ProjectGenerate

Hi everyone,I have a screen project displaying a camera image using an STM32N6. I've validated and run several peripherals like DCMIPP and DMA2D. I'm currently displaying a 720x576 resolution image from DCMIPP on the screen via layer 2 using bitmap addressing.My question is: Since I'm using internal RAM, Touchgfx uses one layer, and one layer is used for the camera. Because I'm not processing any bitmaps and need space, I've significantly reduced the size of the cmd_list area. After adding all this, I have about 300kB of free RAM left.Now, what I need is to be able to see this camera image in full size on my 1024x600 px screen. However, I want to know if this enlargement is possible and if it requires a cmd_list, i.e., vector graphics.Will I use vector graphics for this? Will GPU2D use the RAM allocated for layer 2 for this operation, or will it require an additional amount of RAM equal to the screen size? Best Regards,Onur 

We are currently using LPTIM1 to measure the time period. As this operation needs to be performed frequently, we are using the following APIs:   HAL_LPTIM_TimeOut_Stop_IT(&hlptim1) HAL_LPTIM_TimeOut_Start_IT(&hlptim1, 0xXXXX, 0xXXXX)   During this process, the LPTIM_Disable() function temporarily disables all interrupts using PRIMASK while waiting for the LPTIM_FLAG_ARROK and LPTIM_FLAG_CMPOK flags.   This global interrupt masking is causing data loss on LPUART1, which is operating at 115200 baud. As a result, we are encountering ORE (Overrun Error) due to missed UART interrupts.   Given this behaviour, we would like your guidance on the following:   Is it safe to modify the LPTIM_Disable() implementation by removing or commenting out the PRIMASK-based global interrupt disable? Alternatively, is there a recommended approach to avoid this blocking behaviour while still ensuring correct LPTIM operation?   We are concerned about maintaining real-t

Hello,I'm trying to write to configuration register of P3T1750 sensor, I can perform this with I2C protocol but it not successfully with I3C, the sensor still ACK the write command but it NACK the read command to configuration register. With the temperature register i can read value with I3C.I just want to confirm that this is I3C/I2C sensor but the configureation register only r/w by I2C controller, right?

Hi,while integrating the module, we noticed that UDP client connections appear to be explicitly blocked in the driver (w61_at_net.c) for mission_t01 firmware (LwIP offload). The following code only allows TCP and SSL connections:if ((conn->Protocol != W61_NET_TCP_CONNECTION) && (conn->Protocol != W61_NET_TCP_SSL_CONNECTION) #if (W61_NET_IPV6_ENABLE == 1) && (conn->Protocol != W61_NET_TCPV6_CONNECTION) && (conn->Protocol != W61_NET_TCPV6_SSL_CONNECTION) #endif /* W61_NET_IPV6_ENABLE */ ) { NET_LOG_ERROR("Only TCP and SSL protocols are supported for client connections\n"); return W61_STATUS_ERROR; }However, according to the official AT command documentation, UDP client connections are supported:https://applist67.github.io/Web_AT_Documentation_ST67/v2.0.106/index.html#establish-udp-connectionAfter commenting out this restriction, I was able to establish a UDP client connection successfully, and communication seems to work.Is there a specific reason why

I am trying to build a custom Yocto Scarthgap image for a custom STM32MP153CAA3 board.I have followed the guide at https://wiki.st.com/stm32mpu/index.php/How_to_create_your_own_machine but have several issues.I have created a configuration in CubeMX 6.15.0 and exported the DTB into my project.When I try and build I get an error in u-boot ERROR (phandle_references): /soc/rcc@50000000: Reference to non-existent node or label "clk_hse"(along with references to other clock nodes)I do a `devtool  modify u-boot-stm32mp`  to get at the source code and follow through the DTB The includes from the u-boot DTB file from CubeMX are:#include "stm32mp153.dtsi" #include "stm32mp15xa.dtsi" #include "stm32mp15xxaa-pinctrl.dtsi" #include "stm32mp15-m4-srm.dtsi" #include "stm32mp15-scmi.dtsi"stm32mp153.dtsi includes stm32mp151.dtsi which references the clocks, which is great.However the last include, stm32mp15-scmi.dtsi then goes and deletes them all!/delete-node/ &clk_h

Hi STM Forum,I'm integrating a custom QSPI display controller with TouchGFX and ThreadX. I need to convert the TouchGFX framebuffer into RGB666 (6 bits per color) for a custom display interface that runs over SPI/QSPI.Here is my IOC. As you can see, I currently have only the QSPI and the clock connected.   I believe the framebuffer is defined in TouchGFXGeneratedHAL.cpp as:LOCATION_PRAGMA_NOLOAD("TouchGFX_Framebuffer")uint32_t frameBuf[(320 * 240 * 2 + 3) / 4 * 2] LOCATION_ATTRIBUTE_NOLOAD("TouchGFX_Framebuffer")My target app currently runs on an STM32F7. I also have a GFX01M2 display on a Nucleo H503, but the SPI display example is of limited use because it appears to use many more GPIOs than I have available in my application (I only have QSPI).I have the following questions that will help me integrate TouchGFX into this project:How do I invoke a screen switch from code?When and in which method should I capture the framebuffer, manipulate it, convert it, and pass it to

Hello,coming from OpenSTLinux 4.2 (mickledore) we are in the process of migrating to OpenSTLinux 6.2 (scarthgap).The process of how multiple partitions (bootfs, vendorfs, userfs) are "split out" of the rootfs appears to have changed considerably.After switching all relevant meta layers to the commit/version used in OpenSTLinux 6.2, we effectively get bitbake QA errors for every image recipe (even the ones not being built). The errors appear related to the new bbclass "stsplitpartitions".The release notes of OpenSTLinux 6.2 mention the change as "Add image class to split rootfs image on several partitions: ST SPLIT PARTITIONS", but fail to provide any guideline on how to migrate existing projects to the new partitioning scheme.For testing, I removed all our proprietary layers and only kept the ST layers and standard Bitbake/OpenEmbedded layers.But the errors persist even for this minimal setup when building the standard ST image recipe st-image-core.How does st-split-part

Dear all,I have designed a custom board using the STM32H563ZIT6 as the host MCU and the ST67W611M1 as the NCP.As part of the initial bring-up, I am attempting to flash the ST67W611M1 using the QConn_Flash_Cmd-ubuntu tool in standalone mode. For this, I have connected a USB-to-TTL converter directly to the NCP UART interface.The BOOT and CHIP_EN pins of the ST67 are controlled by the host MCU, which toggles them in the required sequence to place the NCP into UART (flash) mode (see below code). I use the same sequence given in the NCP_Loader Example.if (flash) { LL_GPIO_SetOutputPin(BOOT_GPIO_Port, BOOT_Pin); } else { LL_GPIO_ResetOutputPin(BOOT_GPIO_Port, BOOT_Pin); } /* RESET NCP CHIP */ LL_GPIO_ResetOutputPin(CHIP_EN_GPIO_Port, CHIP_EN_Pin); HAL_Delay(100); LL_GPIO_SetOutputPin(CHIP_EN_GPIO_Port, CHIP_EN_Pin); if (flash) { /* CLEAR BOOT */ HAL_Delay(100); LL_GPIO_ResetOutputPin(BOOT_GPIO_Port, BOOT_Pin); }I verified the BOOT and CHIP_EN signals on an oscilloscope, a

Hello,I have recently installed and launched stm32cubeai studio latest version and it appears to be hung at launch screen with progress bar in motion.I have tried to close this from task window and tried uninstalling and installing it but still same issue.restarted the pc as well. What could be the issue. I have still 10 gb of hard disc space left. Br, 

Hello, I used MX2 for the last two weeks and it is a great improvement over MX. I build many small projects with it and I am constantly running into a problem related to timer configuration. I enter the values for the Prescaler and the Counter period as Integers and unfortunately when I close the project and reopen MX2 converts the value to Hex (and indicates that it is a Hex value). I keep forgetting that MX2 does this and I enter a new value as an Int thinking that my selection was sticky. Could you make the Int/Hex selection sticky? It's a small issue but it will save developers some trouble. Thank you,Gil 

Hello everyone,I’m trying to develop a new project using an STM32C552RET6 with a TFT display.I’d like to use TouchGFX for this, but I can’t find any instructions in CubeMX2 on how to configure a project as a graphical application.I saw some examples in TouchGFX Designer using the STM32C5, but I got the impression that the integration was done manually.So, does anyone know if CubeMX2 has this functionality?Thanks,Matheus  

Hello ST Community,I M USING STM32H745I-DISCO (MB1381-H745XI-B02), WHICH COME DEFAULT MII MODE, TO CONFIGURE IT ON RMII, WHAT CHANGES I HAVE TO DO IN HARDWARE, IOC. AS THIS BOARD HAVE ETHERNET IC LAN8742A-CZ-TR WHICH HAVE BOTH MII,RMII PROTOCOLS.AS I HAVE SEEN SOME VIDEOS ON ETHERNET FOR DIFFERENT STM32 CONTROLLER IN RMII, I M NOT ABLE TO GET RESULT.  I WANTED TO KNOW DO THIS BOARD CONFIGURE IN RMII, IF YES THEN TELL ME HOW I CAN DO. HERE IS CONFIGURATION I HAVE DONE IN MY PROJECT.  PG11 ETH_TX_EN ARM Cortex-M7 n/a Alternate Function Push Pull No pull-up and no pull-down Very High n/a   true PG14 ETH_TXD1 ARM Cortex-M7 n/a Alternate Function Push Pull No pull-up and no pull-down Very High n/a   true PG13 ETH_TXD0 ARM Cortex-M7 n/a Alternate Function Push Pull No pull-up and no pull-down Very High n/a   true PC5 ETH_RXD1 ARM Cortex-M7 n/a Alternate Function Push Pull No pull-up and no pull-down Very High n/a   true PC4 ETH_RXD0 ARM Cortex-M7 n/a

It looks like I have the 32F469IDISCOVERY board that looks to be powered ok via USB connector CN13, however the board doesn't appear to have demo software preloaded. COM LED LD6 flashes red. I note on the ST website that there is the 32F469IDISCOVERY compiled demo binary, which I have downloaded. The Readme says: The QSPI external flash loader is not integrated with supported toolchains, it ís only supported withSTM32 ST-Link Utility V3.7 or later. But the ST website says that the ST-Link Utility is NRND and to use STM32CubeProg instead. I've tried the latest version of STM32CubeProg and it can't connect to the board via USB: Error: Establishing connection with device failed. What is the best way of programming the board with this file please? Kind regards, Al

CubeMX 6.17. When creating a new project for H533RETx or for the corresponding Nucleo-H533, SYSCLK is set at 32 MHz.Not sure whether or not it is intended, but it looks like a trap for a new user, since the MCU datasheet talks about 250 MHz.Instead, example projects for Nucleo-H533 (at least the couple that I've seen) quite reasonably run the MCU at 250 MHz, driven from the crystal present on the board.

Hello,I have downloaded the stedgeai for Linux on windows pc and transferred to Linux system running Ubuntu 22.04 .i want to know is it possible to install it in a headless mode where I don’t have to do or click anything on the gui as my Ubuntu system is all console based with no gui.whenever I try to run ./Linux installer I am getting this error ./-linux-onlineinstaller: error while loading shared libraries: libxkbcommon-x11.so.0: cannot open shared object file: No such file or directoryplease let me know how to install it on a headless system.bestR

Dear,When running the FSBL that includes HAL XSPI initialization logic on the Nucleo-N657X0-Q board (MB1940-N657X0Q-C02), the flash erase with the STM32CubeProgrammmer v2.22 sometimes fails. However, if I leave out the XSPI initialization logic for accessing the NOR flash, flash erase always succeeds. BOOT pin 1 is set to DEV and I am loading the FSBL firmware directly into RAM.Do you have any idea why XSPI Init causes the flash erase to fail ?BR,EdwinD