STM32 MCUs

  I have tried using STM32CubeMX 6.17.0 to generate an STM32F429 DISC1 project.The generated project opened in STM32CubeIDE could not be compiled unless I add <root folder> in Project -> Properties -> C/C++ General -> Path and Symbols, the source location tab.I don't know how this happen. It's disturbing to modify project settings each time after modifying the CubeMX and generating the project.It's probably that should happened after I add some source folders to the projects. 

Only 2 of 4 QSPI data lines active during pixel write, despite DMODE=3 confirmed in CCR 이미지 4장을 모두 참조하여 ST Community 문의 글을 작성합니다.EnvironmentMCU: STM32U5G9ZJ (Cortex-M33, TrustZone enabled)IDE: STM32CubeIDEHAL version: STM32U5xx HAL Driver (included in project)Interface: HSPI1 → QSPI LCD (ICNA3306-compatible controller) Hardware ConfigurationGPIO settings are shown in [XSPI_2.png]. All six HSPI1 pins are configured as Alternate Function Push-Pull with GPIO_SPEED_FREQ_VERY_HIGH and GPIO_AF8_HSPI1:Pin Signal Speed PI3HSPI1_CLKVery HighPH9HSPI1_NCSVery HighPH10HSPI1_IO0Very HighPH11HSPI1_IO1Very HighPH12HSPI1_IO2Very HighPH13HSPI1_IO3Very HighClock configuration is shown in [XSPI_3.png]: HSPI1 kernel clock source is set to SYSCLK (160 MHz). PLL1: HSE(16MHz) × PLLN(10) / PLLR(1) = 160 MHz.CubeMX parameter settings are shown in [XSPI_1.png]:Fifo Threshold: 4 bytesMemory Type: MicronClock Prescaler: 1 (→ FCLK = 80 MHz)Clock Mode: Low (Mode 0)Sample Shifting: Half Cycle Problem

Is it possible to connect 8 PDM microphones to the STM32N6 via MDF?

Hello,I am facing an issue with the STM32C5 HAL SPI driver related to CRC error detection.In my setup, CRC is enabled for SPI. When a CRC error occurs, I can observe that the CRCERR flag is set before the transfer is closed. However, the CRC error is never reported via the HAL error callback.Looking into the HAL implementation, I noticed the following behavior:SPI_CloseTransfer() calls LL_SPI_Disable()After disabling SPI, SPI_CloseTransfer() checks LL_SPI_IsActiveFlag_CRCERR()When this check is performed after LL_SPI_Disable(), the CRC error is no longer detectedIf I move the LL_SPI_IsActiveFlag_CRCERR() check before LL_SPI_Disable(), the CRC error is detected correctlyAdditionally, in my case SPI_CloseTransfer() is called from HAL_SPI_IRQHandler(), but:the return value of SPI_CloseTransfer() is not evaluatedonly the Tx/Rx complete callback is invokedmy error callback is never called, even though a CRC error has occurredFrom my understanding:LL_SPI_Disable() itself does not clear the C

This is an improvement request post.STM32 HAL on every family has tons of following code constructs:tickstart = HAL_GetTick(); while (!condition) { if ((HAL_GetTick() - tickstart) > TIMEOUT_VALUE) { return HAL_TIMEOUT; } }When using HAL with (Free)RTOS or interrupt based scheduler, then these while loops delay same priority tasks (until time-slicing kicks in), block everything that has lower preemption priority, waste energy (crucial for battery powered devices) and decrease responsiveness.There are multiple ways to improve it. One of the simplest is to supplement non-critical* loops with optional user-definable yield macros.__weak void HAL_Yield(void) { } tickstart = HAL_GetTick(); while (!condition) { if ((HAL_GetTick() - tickstart) > TIMEOUT_VALUE) { return HAL_TIMEOUT; } HAL_Yield(); }Now user can implement something like this when using CMSIS OS v2 API:#include "cmsis_os2.h" void HAL_Yield(void) { /* Kernel running and call not from ISR? */ if ((osKernelG

Hello, I have a STM32 NUCLEO-N657X0-Q development board. I wanted to interface with 8 digital PDM MEMs microphones.  In section 68.2 of the STM32N6 reference manual, it states that the N6 supports a "PDM interface, supporting up to 4 microphone pairs". Also in section 2.2.3 of AN5027, it states that if 8 microphone want to be used, the recommended data IO lines are SAI_D1, SAI_D2, SAI_D3, and SAI_D4. Using CubeMX, I see no option for microphone pair 7-8. In addition to this, SAI_D4 doesn't exist when I search for the pin.  So how do I interface (if possible), the last microphone pair?  Thanks, Christopher

Hi everyone, I am currently developing an image capture project using the STM32N657 (Cortex-M55) and have encountered an extremely bizarre DMA2D write issue (a silent failure). Goal: Use DMA2D (M2M_PFC) to convert an RGB565 buffer to RGB888 and write it to CPUAXI_RAM1 (0x34080000). [Problem Description] I wrote a "minimal isolation test" to bypass all camera/GPDMA variables. I forced the CPU to fill the source buffer with pure white (0xFFFFFFFF), and then manually triggered the DMA2D to transfer it to the destination buffer. The Result: The DMA2D finishes successfully. The DMA2D->ISR register reads 0x00000002 (the TCIF Transfer Complete Interrupt Flag is set, and there are NO Transfer Errors). However, the destination buffer remains completely filled with 0x00000000. [Troubleshooting Done] To isolate the issue, I have verified the following, but the problem persists: CPU Read/Write Test (Pass): Before triggering the DMA2D, I forced the CPU to write 0xDEADBEEF to the destinatio

Hello, I am working with the following setup: Board: B-L4S5I-IOT-01A MCU: STM32L4S5VIT6 BLE Module: BlueNRG-M0+ (in built in the Kit) I am currently facing an issue related to the BLE MTU (Maximum Transmission Unit) size. By default, the payload length is limited to 20 bytes, which is insufficient for my application, as my data length exceeds 180 bytes. I would like to know: Is there a way to increase the MTU size on the BlueNRG-M0+? Can this be achieved without modifying my existing data transmission mechanism (i.e., without manually fragmenting the data into smaller packets)? My goal is to transmit larger data packets in a single operation, if supported. Any guidance or recommended approach would be highly appreciated. Thank you.

Title edited to clarify this is about CMSIS-RTOSHello, everybody!I don't know where to look for information on which CMSIS versions are supported by specific STM32 microcontrollers. I asked one of the ST employees and STM32 Sidekick about this, and I got no definitive answers.STM software tools confuse me further. For example, STM32CubeMX (6.17.0) allows me to choose CMSISv2 the interface for FreeRTOS in my STM32F769I‑DISCO board project, but LwIP in the same project does not see the operating system used unless I change the CMSIS version to v1 (you can find more details about this specific issue in this thread). I couldn't find any document that would say which interfaces are supported by LwIP either.That's why I would like to ask You, where should I look for information about which CMSIS versions are supported by specific STM MCUs and, ideally, middlewares and software packages?

I am working with STM32N6570-DK. My code is building fine , suddenly a hard fault has started coming. I have tried updating firmware, resetting the board, unplugging and reconnecting it, But debugger is getting stopped after sometime. 

Hello Team, We are using STM32N657X0H3Q for one of our application, while looking for the voltage level information for pins, we did not get any information for PA0 pin for the controller, specifically i am referring the notes column in pin description section. I hope you are getting my question.  RegardsHarsh Bhavsar 

So apparently in 2026, creating a basic embedded C project now requires… a login.Tried spinning up a project in STM32CubeIDE and got a nice “half-built” result:Project created ✔Code generation :cross_mark:Explanation :cross_mark:Turns out the IDE now needs to quietly download the HAL/CMSIS packages, which in turn requires a myST account login… but:It doesn’t tell you thatIt doesn’t prompt you (on Linux at least)It just silently fails and leaves you debugging yourselfSo you end up thinking:“Did I misconfigure the clock? The linker script? The .ioc?”Nope. You just weren’t logged into a website.Nothing says robust embedded tooling like a hidden cloud dependency for generating main.c.Bonus points for the UX where the “login” option is buried under:Help → STM32Cube Updates → Connection to mySTBecause obviously that’s the first place you look when your GPIO project won’t build.Anyway—manual firmware download and local install fixes it. Once you discover the secret handshake.Progress :thumbs_

Hi @Ghofrane GSOURI. I just noticed new STM32CubeMX2. It's for STM32C series currently but I downloaded it to check it out. It looks very nice, that's for sure. Yet this topic is about file format. MX2 re-uses .ioc file extension but it's format is strange. It is made of JSON/Python?? multiline strings containing JSON and YAML. I don't understand what format is it exactly. The data inside it is also hard to understand and there is a lot of clutter, like IDs, URIs, URLs, descriptions, etc. Why on earth would somebody put field description text beside field name and value?If I may express may opinion - this is awful. It's even worse than old format. It won't be easy to merge changes in such file. It looks like it's a mash-up of multiple tools/libraries serialized states. CubeMX developers are going to have backward and forward compatibility problems and end users are going to suffer if bugs emerge.I would like to suggest one more file format: TOMLEdit: Moved from New IOC file f

SDMMC HAL driver implementation is full of timeouts like this:uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); do { if (count-- == 0U) { return SDMMC_ERROR_TIMEOUT; } sta_reg = SDMMCx->STA; } while (SOME_FLAG_NOT_SET);It may work in a single-threaded application on some basic CPU which runs fixed clocks per cycle, but it's not accurate on CPUs with dual-issue pipeline. All preempting interrupts and in case RTOS is used, all higher priority tasks, prolong this timeout. And vice versa - the longer this timeout gets the more it blocks lower priority tasks and interrupts. And the timeout isn't even in microseconds to justify it. SDMMC_CMDTIMEOUT value is 5000 milliseconds (by the comment). It's bad implementation by any standard.It's been so for a long time in many STM32 series (F4, H7, H7RS, N6, etc.). It's reported at least 6 years ago: I may have encountered a bug in SDMMC_GetCmdResp1 ... - STMicroelectronics CommunityI didn't check all the post

Hey Team, Another day with a different problem.We have reached the point where we have to migrate to either XIP or LRUN in the life cycle of our project.We choose to do XIP and set up the External memories appropriately , For this workflow, we are using the the stm32N6DK, and  MX66UW1G45G_STM32N6570-DK.stldr for starters.We have set up the debug session as indicated in the  Getting started with STM32N6 MCUs in STM32CubeIDEAttached are theDebug logs from some of the debug sessions.The content of my linker scripts (FSBL) and (APPLI)Screen shoots of debug configurations . Spoiler (Highlight to read)Our debug sessions fail straight from the beginning as shown int the debug logs.Our debug sessions fail straight from the beginning as shown int the debug logs.Note:  At some point the debug session worked okay,Every time it worked I had not to have break points inserted in the application project.I am currently inclined to think the issue is with the IDE debu

My USB ECM project on NUCLEO-U575 and NUCLEO-U5A5 - it works now, on all OS platforms.https://github.com/tjaekel/STM32U5xx_USB_ECM This project and demo for a STM32U575I-EV (where I have converted from) needs a vendor driver on Windows.Windows does not support USB ECM (or USBLAN, just RNDIS, but it is different). There is not any driver to use USB ECM on Windows, except: Belcarra USBLAN demo driver.Dear STM Team:please, could you consider to license the Belcarra USBLAN driver for Windows?http://usblan.belcarra.com    http://www.belcarra.comIt would be nice, when STM (or AZURE RTOS - Microsoft), providing a demo for USB ECM, that it can be used also on a Windows OS host.Please, license such this driver and provide it together with CubeMX (and demos, HAL drivers). Thank you.Remark:In order to make it really correct working on all OS platforms (esp. Windows OS), a small fix in file "ux_device_descriptors.c" is needed (see the modification in the GitHub projec

I configured a nucleato-L152RE LED program using CubeMX6.17+STM32L1 Firmware Package V1.10.6 and found that the program kept restarting automatically. After adding the following code to the SystemInit() function generated by CubeMX, the problem was solved. What is the reason for this? And my other projects never need to include this line of code, such as F103, F411, G431, L051, and so on.SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET;

Hi I'm using STM32F411RET6 MCU. I tried to connect using the programmer to download the firmware, but there was an error as shown below, and the data cannot be read. 13:18:34 : UR connection mode is defined with the HWrst reset mode13:18:34 : ST-LINK SN : 54FF7106788056521117016713:18:34 : ST-LINK FW : V2J45S713:18:34 : Board : --13:18:34 : Voltage : 3.22V13:18:34 : SWD freq : 4000 KHz13:18:34 : Connect mode: Normal13:18:34 : Reset mode : Software reset13:18:34 : Device ID : 0x43113:18:34 : Revision ID : Rev A13:18:34 : Debug in Low Power mode is not supported for this device.13:18:34 : UPLOADING OPTION BYTES DATA ...13:18:34 : Bank : 0x0013:18:34 : Address : 0x40023c1413:18:34 : Size : 8 Bytes13:18:34 : UPLOADING ...13:18:34 : Size : 1024 Bytes13:18:34 : Address : 0x800000013:18:34 : Read progress:13:18:34 : Error: Data read failed After that, the firmware will not be downloaded, and the message core is locked up.I checked that it was a problem related to RDP, and it wa

I am working with the STM32N6-GettingStarted-ObjectDetection demo.  I found that doing a full chip erase wipes some bootloader code.  I was able to get my project going again by flashing the .hex file that came with the STM32N6-GettingStarted-ObjectDetection demo, the loading my code. Digging around on the net suggested that the prebuilt demo has a bootloader.  I have been unable to locate the bootloader.Can you provide me with the bootloader, preferably as a .hex file?

Hi everyone,I am working on a project using BNO085 IMU sensor and STM32H7A3ZIT6Q. I have a single sensor working but stuck at 44Hz. The same sensor with SparkFun library on ESP32 achieves 1.2ms read time. I need help understanding why and how to match ESP32 performance on STM32.Hardware:NUCLEO-H7A3ZI-Q (STM32H7A3ZIT6Q, Cortex-M7 @ 280MHz)Adafruit BNO085 breakout boardI2C on PB8 (SCL), PB9 (SDA), PC0 (INT pin)P0 and P1 tied to GND (I2C mode, address 0x4A)Software:STM32CubeIDE with HALOfficial CEVA SH2 library from github.com/ceva-dsp/sh2REPORT_INTERVAL_US = 2500 (targeting 400Hz)SH2_ROTATION_VECTOR (9-axis full quaternion)STM32 performance achieved so far:I2C 400kHz polling: 28Hz, read_ms = 32msI2C 1MHz Fast Mode Plus: 44Hz, read_ms = 19msINT pin wait inside sh2_hal_read(): still 44Hz, read_ms = 19msESP32 performance with same sensor and SparkFun SH2 library:read time: 1.2msData rate: close to 400HzThis is a huge difference. 19ms on STM32 vs 1.2ms on ESP32 with the same SH2 library unde

Hi, I am using STM32U385CGU6 with 1.8V supply. My GSM peripheral using the 3.3V Uart port for a dedicated time (2sec) then turn back to 1.8V level of UART.  Could you offer 3.3V tolerant pin? I am using PA8 to communicate with GSM module. thank you & best regards, feramuz karşil 

When calling HAL_QSPI_Abort() to disable memory mapped mode, with the memmap timeout active, I find that there is a race condition that can cause the abort to fail when it should not. If the memmap timeout happens after the abort function's check of the busy flag, but before it can write to the abort bit, the TC flag will never be set and the abort function will wait for the configured qspi timeout, then return an error.I am testing this on a STM32F769I-DISCO board.I have found that the following patch will fix the issue: diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c index 8404466..01a06ca 100644 --- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c +++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c @@ -2381,19 +2381,19 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /* Configure QSPI: CR register with Abort request */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABOR

Heyho,using L073 at 32MHz, so even I2C transfers "seem" fast, at least in "fast mode plus" at SCL 1 MHz. And I don't want to over-use clock stretching.I'm looking for a way to use I2C slave receive with DMA, but an unknown transfer length.Right now it looks to me as if I could do the following:I2C & DMA prep: all stuff & addresses set, DMA in I2C enabledon I2C ADDR match interrupt:set DMA CNDTR to max buffer lengthenable DMA on I2C STOP match interrupt:disable DMAAny problems with that?Have only 1 device for now...Thanks!

One of my friends noticed, that ST NRND'd not only the STM8, but also the whole STM32L1xx family.However, in contrast to STM8, the 'L1 are under the 10-year commitment program, so they should continue to be available in the next 9 years. JW

Hi,I've have to port an existing huge application from F4 to a H753 board. The F4 has PNOR the H7 dual QSPI flash.One task parses XML configuration data from PNOR flash. A second task stores data e.g. log data in same PNOR.Parsing configuration data use of string functions which require a memory address, while writing to QSPI requires indirect mode. This would require kind of flash memory management, which I guess is bit tricky to handle.I started using indirect mode only and DMA to read chunks of data into memory buffers before parsing it. This works fine. A QSPI read request can suspend an ongoing erase operation, so it is not blocked or delayed. Great.But compared to the PNOR read, the latency when reading data chunks into buffers in indirect mode drops the data processing performance. Therefore I want to check if using memory mapped mode is worth some time spent for investigations.I've read that QSPI read has a prefetch buffer. Is this mechanism available for data read too or only