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Hi everyone,I’m exploring whether an STM32 board can be used as a reliable USB HID host/device tool to measure mouse movement data more accurately, especially for things like polling rate, raw movement counts, and possibly estimating DPI/CPI consistency.My main questions are:Is STM32 a practical choice for capturing USB mouse HID reports with enough timing accuracy for this kind of analysis?Would this be better implemented in USB host mode, or as a USB device/proxy setup?Are there any STM32 examples, middleware recommendations, or timing limitations I should be aware of for high-frequency mouse input analysis?If someone has worked with HID polling intervals on STM32, what is the best way to log and validate the incoming report rate?For context, I built a small browser-based reference tool here : https://mouse-dpi-analyzer.com/  I’m not trying to promote it, only sharing it so you can see the kind of measurement workflow I’m trying to improve with hardware support.I’d really a

I was trying to implement emulated EEPROM and I think I set the EEPROM page area right into the critical option bytes area. Notably, this didn't happen until I added the actual eeprom_emul.c and flash_interface.c files into the cmake configuration, compiled and flashed the program once. This obviously makes a call to "HAL_FLASH_UNLOCK()" so I think it's pretty messed up. Either way, after this, I could not flash the chip beyond 0x80000050, additionally, it would instantly lock up on boot. I believe my Option Bytes were also grenaded.  PCROP_RDP turned itself on, ESE turned itself on and the rest I am unsure of changes. Either way, I managed to turn off RCROP_RDP by setting RDP to 1 and then to 0. After this, flashing the chip, fills every line with the same repeating nonsense bytes. So I think write protection is disabled, but it's still uploading nonsesen. Notably, trying to hit "full chip erase" does not work, and just hangs. Now ESE remains checked. When trying to uncheck

HI ALL.I am using MB1549C board with NUCLEO-U5A5ZJ-Q cpu.SD card is connected to SDMMC1 pins 4bit mode.HAL code is generated with CUBE MX.During SD card initialization CMD8 command is sent.I see that after it sent some flags are set which relates to DPSM.But CMD8 does not require data transfer on D0 pin.So DPSM must not be enabled. But I see these flags in STAR register.BUSYD0,DPSMACT,DTIMEOUT.Response is received correctly but why DPSM is enabled and of course timeout error occur becausethere is no and should not be data on D0?Thanks

Hi all,I'm having an issue with a pre-existing project. It was initially built a few months ago on version 1.16 of the IDE, and confirmed to be working. I have since updated to stm32cube ide version 2.1, and am having an issue with this project not being able to launch.  The projects builds with zero warnings or errors as expected, but on trying to flash my board I get "Unable to launch. the selection cannot be launched, and there are no recent launches".    One change I made (that I'm not sure if it is relevant) is updating the GCC flags to inlcude "-Wno-implicit-function-declaration", as it was having trouble finding a C wrapped extern method.  I have seen a previous thread that resolved this issue by using the example importer (Solved: Unable to launch, The selection cannot be launced ... - STMicroelectronics Community), but I want to avoid that to prevent any unintended changed to the current project structure. Additionally, unless I have a m

Hi I am trying to set up hardware SPI using the following. My software SPI works fine, but the hardware SPI doesn't even have a clock signal.   /** ****************************************************************************** * @file : main.c * @brief : P7-SPI2: Two bursts, same 6 bytes. Burst1: SW SPI (PE2/PE6). * Burst2: Hardware SPI1 (PA5/PA7). Probe D0=PE2, D1=PE6, D2=PA5, D3=PA7. * HW SPI1: kernel clock per_ck, GPIO before SPI, CSTART errata workaround. ****************************************************************************** */ #include <stdint.h> #define RCC_AHB4ENR (*(volatile uint32_t *)0x580244E0u) #define RCC_APB2ENR (*(volatile uint32_t *)0x580244F0u) #define RCC_D2CCIP1R (*(volatile uint32_t *)0x58024450u) #define GPIOA_MODER (*(volatile uint32_t *)0x58020000u) #define GPIOA_AFRL (*(volatile uint32_t *)0x58020020u) #define GPIOA_ODR (*(volatile uint32_t *)0x58020014u) #define GPIOE_MODER (*(volatile uint32_t *)0x58021000u) #define GPIOE

Dear all,I'm trying to get a VD55G0 sensor (promodule connected via P-board) working on a Raspberry Pi 5. I followed the Linux Start Guide for the driver. The only difference with respect to the guide were the name of the device tree file (guide says pcb4189.dts which the repository does not contain, so I used pcb4189_vd55g0.dts), and the names of the libcamera packages (the filenames seem to have changed, I have installed both .deb packages from the STSW-IMG505_RPI download). However, the camera sensor is not detected at all:$ rpicam-hello –-list-cameras [0:12:15.584143721] [1262] INFO Camera camera_manager.cpp:340 libcamera v0.0.0+5981-73aeb895-dirty (2025-12-09T14:49:21UTC) Made DRM preview window Preview window unavailable ERROR: *** no cameras available *** $ ls /sys/bus/i2c/drivers dummy stmpe-i2c $ uname -r 6.12.62+rpt-rpi-2712There is some output in the system log regarding the sensor, but I'm not sure what to make of that:$ sudo dmesg | grep vd55g0 [ 0.938491] /axi/pcie

Hi, I have a custom STM32N6 board where the BOOT0 and BOOT1 pins are tied directly to ground under the BGA with no test points or jumpers. Is there anyway to connect a debugger in this scenario or is my board bricked? Below is what I get when attempting to connect via an ST-Link V3: >STM32_Programmer_CLI.exe -c port=SWD mode=UR -rst ------------------------------------------------------------------- STM32CubeProgrammer v2.21.0 ------------------------------------------------------------------- ST-LINK SN : 003700163431511731343632 ST-LINK FW : V3J17M10 Board : STLINK-V3MINIE Voltage : 3.26V SWD freq : 8000 KHz Connect mode: Under Reset Reset mode : Hardware reset Device ID : 0x486 Revision ID : Rev Z Device name : STM32N6xx Device type : MCU Device CPU : Cortex-M55 BL Version : -- MCU Reset Error: Unable to run MCU! Error: Error code: 32 And this is what I get from the STM32CubeProgrammer GUI: 23:21:41:351 : UR connection mode is defined with the HWrst reset mode 23:21:41:372

Hi everyone,I tried to manage the USAR LIN break detection interrupt using only HAL driver functions but I did not find a way to do that. I had to modify the file stm32f0xx_hal_uasrt.c adding some code to manage the LIN break interrupt.Is there a way to detect the LIN break in my application without modifying the driver code?This is the code I added to the aforementioned HAL driver file:// At the beginning of the file, where other prototypes are placed   #if defined (USART_CR2_LINEN) extern void HAL_UART_LINBreakCallback(UART_HandleTypeDef *); #endif   //...   // Inside function HAL_UART_IRQHandler   #if defined (USART_CR2_LINEN) /* UART LIN break has been detected ----------------------------------------*/ if(isrflags & USART_ISR_LBDF) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_LBDF); /* Call the callback function to signal LIN break detection */ HAL_UART_LINBreakCallback(huart); } #endif /* USART_CR2_LINEN */If the function is currently unavailable, is

Hi, I have created a project in STM32CUBEIDE for STM32U575ZITQ for USB CDC. I am getting an 85 | HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18); | ^~~~~~~~~~~~~~~~~~~ | HAL_PWREx_PVMConfig ../USB/Core/Src/usbd_conf.c:85:68: error: 'PCD_SNG_BUF' undeclared (first use in this function) 85 | HAL_PCDEx_PMAConfig((PCD_HandleTypeDef*)pdev->pData , 0x00 , PCD_SNG_BUF, 0x18);   I am following the link below to create the project: https://community.st.com/t5/stm32-mcus/how-to-use-stmicroelectronics-classic-usb-device-middleware-with/ta-p/599274   I have tried with USBX but no result. After that I followed above link to create a USB CDC project.   Regards, Abhishek

Hello, We have found that, in an OS context, if two tasks change the configuration of different GPIOs belonging to the same port, then the register can get corrupted due to a RMW race.It seems the RMW operations are not protected:// stm32u5xx_hal_gpio.c :232 tmp = GPIOx->MODER; tmp &= ~(LPGPIO_MODER_MOD0 << position); tmp |= ((pGPIO_Init->Mode & GPIO_MODE_OUTPUT_PP) << position); GPIOx->MODER = tmp;Our solution is as follows:ATOMIC_MODIFY_REG(GPIOx->MODER, (LPGPIO_MODER_MOD0 << position), ((pGPIO_Init->Mode & GPIO_MODE_OUTPUT_PP) << position));Is there any reason why these operations were not atomic in the first place ?Do you see any issue with our solution ?Is there a better way to handle this ?

Hi, I want to go to sleep/stop mode with STM32 and wake on interrupt. After last interrupt it should wait for 10sec and go back to sleep. But I see an edge case where interrupt could occur just before going to sleep/stop mode.How do I handle interrupt just before going to sleep/stop mode (cancel sleep/stop mode)?Basically force WAKE from sleep/stop mode even if STM32 is not yet in sleep/stop mode?  #define STAY_WAKE_FOR_TICK 10000 static volatile uint32_t GoToSleepAfterTick; void main(void) { //... while (1) { HAL_SuspendTick(); HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI); HAL_ResumeTick(); while (HAL_GetTick() < GoToSleepAfterTick) { //... } // interupt could occure here??? } } void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { if (GPIO_Pin == CALL_Pin) { GoToSleepAfterTick = HAL_GetTick() + STAY_WAKE_FOR_TICK; } }   

Hello Team,We have faced the Firmware ( hex file ) theft by Reverse engineering , Our competitor 2 Times. Yes, Two times , while RDP1 is set. We do not have contarct Manufacture in our whole process.Even Reading / Comparing intertlock of 96 bit UID failed.MCU is STM32F303.Can any one suggest a very high Strong Method which ensue complete guarantee for Firmware Protection from any threats. ?It seems STM32 is so famous that , its weak-leak point also Known.Getting Assembly / might be "C" code from Hex file looks Staright forward to crackers.

Hello. I have the following problem. When I enable flto optimization in a (freshly generated) project, several dozen warnings appear during compilation.Sample warnings:Drivers/STM32L4xx_HAL_Driver/Src/subdir.mk:88: warning: pattern recipe did not update peer target 'Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.su'.Drivers/STM32L4xx_HAL_Driver/Src/subdir.mk:88: warning: pattern recipe did not update peer target 'Drivers/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.cyclo'.This problem was not present on the previous version 1.13.2How to solve this problem?

May be somebody know  whats happen with .cproject, .project files after reinstallation STM32CubeMX, STM32CubeIDE, last version and after some other?! Project (at screen behined) is in the folders TochGFX. Told that need plagin ...mcu.ide2.7...  from folder CubeIDE, but if i am set it version than that its files the same i.e not change.I am tried set in propertis its file "open cross STM32CubeIDE " but  in CubeIDE open only .cproject or project (single) files but not all of the project as early.Thanks. 

I'd like to validate ST1VAFE3BX vAFE measurement data against test signals as part of hardware design validation of a custom ECG sensor design based on ST1VAFE3BX. I intend to input reference signals (differential or single ended) into the two bio channels of the ST1VAFE6BX, capture the raw ADC data, convert to mV, and then compare to the reference signals.- Conducting this test will help validate the data processing, especially reading and interpreting vAFE data from the FIFO, which is different than if reading from registers.Are there any documents or guides for how to do such tests?Currently the vAFE waveforms I capture look correct except for the amplitude. 

Hi, I have all configured using internal loop FDCAN1 and there is not working on my STM32G474RE-Nucleo board 

When I open Help -> Manage Embedded Software Packages in STM32CubeIDE 1.8.0, I'm unable to click the arrows to expand the package versions under each STM32 family. If I click the "+" icon in the top right corner, everything expands, but then I'm unable to check any of the boxes next to the packages to select them.  FYI, I do not have any of these problems in the standalone STM32CubeMX 6.4.0: I'm running this on macOS Monterey 12.2.1 running on Apple Silicon (arm64).

I downloaded the package from here: https://www.st.com/en/embedded-software/x-cube-azrtos-h7.htmlIt is not yet available on MX when searching for example code. Anyways, so I am able to run the UX_Device_Recording which is cool. I notice that it uses the onboard mic, which is  AudioInInit.Device = AUDIO_IN_DEVICE_DIGITAL_MIC; But I want to use the analog microphone that comes with the headset - available in CN17. So I change it to  AudioInInit.Device = AUDIO_IN_DEVICE_ANALOG_MIC;And now it's giving a static noise, but no mic input is captured.  Any idea why?

 I need support to get IAP over SPI.I've esp connected to my stm32u5 over SPI. Stm is slave and ESP is master. For stm I've created project using stmcube by entering MCU part number.Now here my question is1. Do I need to develop bootloader code to achieve this.2. How do I customise bootloader code.3. STM boot pin is connected to ESP. do I need to control this?4. Hwi do I adjust my memory or linker file

Hi,I have this question because the reference manual states:“When flash high-cycle data area on Bank1 is enabled, the code memory map is not continuous from Bank1 to Bank2 on 2M- and 512K-byte devices.”So, does this mean that enabling high-cycle data sectors as EDATA on a 1MB device does not affect the code memory space, while on 2MB and 512KB devices, some sectors are reassigned for EDATA usage? If that’s the case, it seems like the 1MB device effectively has an extra 96KB of high-cycle data memory.Snaku

Hi, I'm building a medical device that will use an STM32 MCU and requires secure boot and secure firmware updates (over USB-C preferably). I have little experience with implementing secure bootloaders, and am looking for a solution that could allow me to get secure boot working out-of-the-box with minimal setup. I've seen that SBSFU offers example projects for secure boot on some MCUs, while MCUboot is also available for some others. It also looks like the STM32U5 series supports their own secure firmware updates based on AN4992. What's the difference between all of these solutions? Out of all the solutions ST offers for secure boot, which ones are the newest/recommended and easiest to get set up with? Because I'm looking for a low-cost MCU, I've identified the STM32L471, STM32L476, and STM32U575 as potential candidates that could support secure boot, but I'm lost as to how to actually set it up or what software solution to use. I'd love to hear anyone else's suggestions for other MCUs

In STM32Cube_FW_H7RS_V1.3.0, file Projects/STM32H7S78-DK/Applications/ROT/OEMiROT_Boot/Inc/flash_layout.h:The macro OEMIROT_LOAD_AND_RUN has 3 possible settings, and we're using the NO_LOAD_AND_RUN to execute code (in external flash) in place.However, we're also using external RAM in our application, and this must be enabled in the bootloader, as the app attempts to initialise values in external RAM at startup.Unfortunately, the external RAM is only initialised if you select LOAD_AND_RUN_EXT_RAM.There is a workaround: in boot_hal.c and low_level_ext_ram.c, replace every instance (3 in each file) of:#if (OEMIROT_LOAD_AND_RUN == LOAD_AND_RUN_EXT_RAM)...with something like:#if 1// (OEMIROT_LOAD_AND_RUN == LOAD_AND_RUN_EXT_RAM)For the future, would you consider having an option to run in place and enable external RAM?Thank you.  

We are seeing a very odd data corruption issue which is highly repeatable, and appears to be related to a configuration setting which we haven't yet identified.In our system (running on an STM32H7S7), we're using the STiROT + OEMuROT secure bootloader to load our application. After a minute or two, the application causes a hard fault.The issue comes down to a POP instruction. I can see in the debugger that a value is being copied from the stack to a register, but one of the bits is flipped. Subsequent instructions do some indirection which ultimately causes the hard fault.It's always the same instruction in the same line of code. It always occurs within the first minute or two of execution.Using the debugger, we can see that the value in the stack (stored in DTCM) is correct. The error occurs when it's copied to the register. And although the error always occurs at the same address, it doesn't appear to be a fault with that location, as when I moved the stack to elsewhere in DTCM,

ST moderator has edited this post to be compliant with the community rules. In next time please use </> button to paste your code. Thank you for your undersranding.   Hello collegues. LL library. Can you help with RTC domain in STM32C031T6. Problem is that, RTC start and counting, I set alarm A evry 1s. This wokrs fine. I'm counting moreless about 30min. After push the pin RESET, RTC starts counting from 0, I want to continue counting ? Initialization code below: void MX_RTC_Init(void) { /* USER CODE BEGIN RTC_Init 0 */ /* USER CODE END RTC_Init 0 */ LL_RTC_InitTypeDef RTC_InitStruct = {0}; LL_RTC_TimeTypeDef RTC_TimeStruct = {0}; LL_RTC_DateTypeDef RTC_DateStruct = {0}; LL_RTC_AlarmTypeDef RTC_AlarmStruct = {0}; if(LL_RCC_GetRTCClockSource() != LL_RCC_RTC_CLKSOURCE_LSE) { FlagStatus pwrclkchanged = RESET; if (LL_APB1_GRP1_IsEnabledClock (LL_APB1_GRP1_PERIPH_PWR) != 1U) { /* Enables the PWR Clock and Enables access to the backup domain */ LL_APB1_GRP1_Enabl

We had:An STM32H7Sx with an external flash on one XSPI port, and an external RAM on the other;Both external devices memory mapped;The core clock running at 380 MHz.XPI1 mapped to port 2, and vice versa.XSPI clock running at 200 MHz.Using our adapted version of ST's secure bootloader, we erased sectors of the external flash, but found that this consistently caused corruption in the external RAM, and it also looked like the erases weren't fully successful either.The driver code which carried out the erases removed the flash from the memory map before each operation, and added it back afterwards.We found that to avoid the RAM corruption, it was necessary to also remove the RAM from the memory map before the flash erase operation, and add it back afterwards.We had assumed that the two buses were independent (despite meeting in the XSPIM), so this result was unexpected; and it's still not clear to us why an erase operation in the flash would cause corruption in the RAM.Also, this probl