STM32 MCUs

I am planning to do an aging test which need capture the voltage of a net, but i found STM32U585OIY6QTR report a value about 40 while the actual voltage of ADC channel is close to VREF.Then i write a simple ADC demo to verify ADC configuration, and run my code on B-U585I-IOT02A board(based on STM32U585AII6Q), it report a correct value, but the same code report a wrong value on my board.I use ADC1  CHANNEL2(GPIOC GPIO_PIN_1) on both board.The only difference between B-U585I-IOT02A and my hardware is the different VREF i think(B-U585I-IOT02A use 3.3V, but my board use 2.5V).Is there any difference on ADC usage between STM32U585AII6Q and STM32U585OIY6QTR?You can find my ioc file and code in attachment, can anyone help me check my configuration? 

Hello,My STM32H573I-DK board is bricked after a failed provisioning attempt.What happened:Accidentally changed PRODUCT_STATE from Open (0xED) to 0x17 (Provisioning) via programmerThen an AI coding assistant (Copilot) attempted some configuration via DFU mode and enabled TrustZoneI no longer have access to the PC where this was doneCurrent symptoms:SWD: "Unable to get core ID", "Cannot connect to access port 1"DA discovery (debugauth=2): "The target is unable to boot on RSS_DA or is in OPEN mode"DA regression (debugauth=1) with default STM32CubeFW_H5 keys: "Unable to detect DBGMCU Mailbox" or "unable to boot on RSS_DA"DFU (USB0): "Target device not found" (with boot jumper set to SYS/MEM)UART bootloader: timeoutWhat I tried:SWD with HOTPLUG, UR, HWrst, ap=0, freq=100DA regression with default key_3_leaf.pem and cert_leaf_chain.b64regression.bat from ROT_Provisioning\DADFU via User USB (CN17) with JP4 on USB-PD positionUART via ST-Link VCPSetup:Board: STM32H573I-DKSTM32CubeProgrammer: v2

Hi AllMaximum input voltage for this series of MCU per Table II of the datasheet is specified to be 4.0 VDC for all pins other than five-volt tolerant. Table 12 specifies the maximum injected current for all pins other than five-volt tolerant to be +/- 5 mA.Given the above specifications would it be permissible to exceed the maximum input voltage if the injected current is limited to lets say 0.1 mA by a resistor in series with the non five-volt tolerant I/O pin? If not what would be the reason?Regardsik

I am trying to develop a small scale lorawan app on a nucleo-wl55jc using the application example in stm32cube_fw_wl_v1.5.0 and have spent several hours trying to trace my error/bug in the software. All join attempts fail because the deveui as it appears in the se-identity.h file is ignored and the mcu derived value applied. Tracing this value to the lora_app.c file shows the se-identity.h file is correctly read and the macro expansion appears to give the correct value in the set user credentials section (lines 617-620) but the join is attempted using what I believe to be the mcu derived value. The same credentials work as expected when used under stm32cude_fw_wl_1.4.0 At the outset, I must confess it's 25 years since I did any serious programming so I may of missed something obvious but I would be grateful for any pointers as to why it's failing!  

Hello! I have been using the STM32H723ZG Nucleo board and am now trying to ping the STM32 device from a PC through an Ethernet connection, but the ping is not working. For ex: ping 192.168.10.XX (STM32 Static IP) No response is received. My board setup and module details are given below.Board / Setup MCU: STM32H723ZG (Nucleo) Interface: Ethernet (RMII) PHY: (e.g., LAN8742 – please confirm) Stack: lwIP (CubeMX generated) RTOS: FreeRTOS Connection: Ethernet cable through splitter (PC ↔ STM32) PC IP: 192.168.10.XX (static) STM32 IP: 192.168.10.XX (static) STM cube IDE version: 1.18.1 Observed Behavior (STM32 side logs): STM32 successfully receives ARP requests from PC.           Who has 192.168.10.50? Tell 192.168.10.100 (Captured by wireshark).      2. lwIP processes the request and generates an ARP reply.      3. ARP reply frame content (from debug log):           192.168.10.XX is at 00:80:XX:X

  I have already set the MTU to 3000 on the PC side. On the STM32H743 side, I have set the RXBUFFLEN, MTU, PBUF_POOL_SIZE, and other related memory configurations to 3000. I have configured and enabled Jumbo Frame and disable Jabber disable and Watchdog disable with ETH->MACCR |= (ETH_MACCR_JE | ETH_MACCR_WD | ETH_MACCR_JD | ETH_MACCR_GPSLCE);However, when I ping the STM32 from the PC with 1472 bytes, it is successful, but pings larger than 1472 bytes fail. Why is this happening? What have I not configured correctly?  

Hello,After spending several days investigating this topic and reviewing all the documentation I could find, I am still completely stuck on how to proceed with implementing STiROT + OEMuROT on my STM32H7S3.An important point is that I am trying to add this security architecture to a project that is already at a fairly advanced stage of development. The project was originally built on top of the XIP template provided by ST:https://github.com/STMicroelectronics/STM32CubeH7RS/tree/main/Projects/NUCLEO-H7S3L8/Templates/Template_XIP The difficulty comes from the fact that, in the XIP context, the project only includes these layers:AppliBootExtMemLoaderAs a first step, I imported ROT_Provisioning into the project in a separate folder. However, I still do not see how I should properly integrate or adapt the following components into my current project structure:OEMiROT_AppliOEMiROT_BootSTiROT_AppliSTiROT_BootShould I try to merge the `*_Appli` projects into my existing Appli context, and

  Hello, I am working on STM32 NUCLEO-G431RB using STM32CubeIDE and FreeRTOS (CMSIS-RTOS v2). I am trying to implement the following requirement: Requirement ADC1 → 1 Channel using Interrupt ADC2 → 7 Channels using DMA Both should run simultaneously with FreeRTOS ADC Configuration ADC1 (Interrupt) Single channel (PA0) Using HAL_ADC_Start_IT() Used for detecting external voltage Expected Behavior: When I connect external power supply to PA0 PA0 should show voltage value Remaining 7 channels should show 0 Example:     PA0 = 2.5V (Interrupt)PA1 = 0PA6 = 0PA7 = 0PC0 = 0PC1 = 0PC2 = 0PC3 = 0       ADC2 (DMA) 7 Channels: PA1 PA6 PA7 PC0 PC1 PC2 PC3 Configuration: Scan conversion enabled Continuous conversion enabled DMA circular mode Using HAL_ADC_Start_DMA() Expected Behavior: If I connect external voltage to PA1     PA0 = 0PA1 = 2.5V (DMA)PA6 = 0PA7 = 0PC0 = 0PC1 = 0PC2 = 0PC3 = 0   &nb

Hi ST Team,I'm creating project in the motor control workbench,I had selected hardwars are1. STM32G4EVAL1 Board2. Motor Drive3. Motor once i selected in the tool as shown in below.in this connector are not available to connect to the main board to motor drive.need to import the .Json file but in portal there is .Json file.This connector (X-NUCLEO-IHM09M2) is needed to use .Could you please help me on this connector how to download from st website. 

When connecting to our stm32n6 using a stm32 Programmer we get an unstable connection. Connecting with a low clock rate (5khz instead of 8000khz) improved the Issue but there still isn't a reliable way to connect to the board. Some retries are needed to get a connection. Also after some time the connection doesnt work entierly and the MCU needs to be powercycled.  

Hi everybody,I read 15 analog channels with DMA on my STM32f446. It works very well (It's tiggrered by TIM3 every 200ms).So I'd like to add Vbat. First, I've added it as the 16th channel of DMA, it works, but I saw the battery voltage decreases (around 0.05V in two hours), so I think I read it too often.So I'd like to read it periodically (every minute for example).I'm trying to read my 15 first channels with DMA and then a classic read for Vbat, but the value is always wrong (around 560 instead of 1000).Is it possible to do that (two different means to read ADC) ?Thank you,

Hi!My application requires NIST-compliant random number generation, and I see some unclear/contradicting info on the Reference Manual, the AN4230 application note, and the public NIST certificate. My MCU is STM32H563ZI.- Reference Manual: https://www.st.com/resource/en/reference_manual/rm0481-stm32h52333xx-stm32h56263xx-and-stm32h573xx-armbased-32bit-mcus-stmicroelectronics.pdf- AN4230: https://www.st.com/resource/en/application_note/an4230-introduction-to-random-number-generation-validation-using-the-nist-statistical-test-suite-for-stm32-mcus-and-mpus-stmicroelectronics.pdf- Public NIST certificate E163: https://csrc.nist.gov/CSRC/media/projects/cryptographic-module-validation-program/documents/entropy/E163_PublicUse.pdf Confusing/contradicting info:- E163 gives a RNG_CR of 0x08F01EXX, but AN4230 says value should be 0x00F01E00 (note difference in bit 27). Also, manual says bit 27 "must be kept at reset value.".- Reset values on the manual do not match my

Dear all,I have been modifying the VENC_SDCard_ThreadX example and wanted to start some activity based on the user button, triggered by interrupt using the usual HAL + BSP helpers to init the gpio, and registering a handler function for falling flanks.So I tried BSP_PB_Init(BUTTON_USER1, BUTTON_MODE_EXTI);and implemented BSP_PB_Callback(). Symptom: Hitting the button turned the program to be stuck in some unrelated irqhandler (debugger name-clash -- the defaulthandler triggered), the callback has not been triggered.I had a look at the BSP implementationn and retried the same with HAL functions, same effect, this code in BSP_PB_Init() sparked my interest: (void)HAL_EXTI_GetHandle(&hpb_exti[Button], BUTTON_EXTI_LINE[Button]); (void)HAL_EXTI_RegisterCallback(&hpb_exti[Button], HAL_EXTI_COMMON_CB_ID, ButtonCallback[Button]);which registers a callback,  and further down the line in stm32n6xx-hal-driver-exti.c there is an HAL_EXTI_IRQHandler  implementation which

Hi ST team,I am seeing what appears to be a silicon-level issue on STM32H563RGV6, revision X, related to the SWAP_BANK option byte.When SWAP_BANK is enabled, a USB OUT endpoint stops being re-armed during a flash mass erase of the inactive bank. The USB ISR still executes, but the BULK OUT path wedges because the OUT endpoint is no longer re-armed. Once the mass erase completes, the endpoint behavior returns to normal.Key observations:MCU: STM32H563RGV6Revision: XThe issue is specifically tied to SWAP_BANK being setThe problem occurs during mass erase of the inactive bankThe symptom is specifically USB OUT not being re-armedThis does not look like a total USB interrupt loss; ISR activity can still occurOther endpoint activity is not affected in the same wayThe entire application, including vector table and read-only data used by the relevant path, is relocated to SRAMBank selection / inactive-bank arithmetic has been verified and is correctThis does not appear to be a normal software i

Hi, I'm using the STM32U5G9J-DK1 Demo Board with the STM Demo Program Ux_Device_DFU, because I need to create a specific bootloader for my board.The STM32CubeProgrammer program connects to the board via USB and I can read its memory, but the program doesn't receive information from the Flash Blocks, so programming doesn't start.If I enable the Bootloader available in the MPU's system memory, the programming via the STM32CubeProgrammer works correctly.What should I change in the STM source code to avoid this problem?Thank you in advanced

Hi,  I have an stm32g473 which use the clock of another system as external clock on PF0 / OSC_IN. This clock is them multiplied by 74 through the PLL. I need to synchronize my code with the external clock (i.e. wait for it to rise).  What is the simplest way to do this? Can I use PF0 both as OSC_IN and as an GPIO in input mode to generate an event on the rising edge? or should I root the clock to both OSC_IN and another GPIO?  Are there other possibilities did not find in the reference manual (e.g. using the HSE as a trigger to one of the timer or an event I could WFE on ?)Thanks.

Hi all, I am currently working with the STM32WLE5JC for a LoRa/LoRaWAN-based IoT node and would like to clarify some points regarding LoRa FHSS and LR-FHSS support. From several discussions in the STMicroelectronics Community, I noted the following statements from ST employees and contributors: “There is no way to activate the frequency hopping as the LoRa stack does not offer this feature on the STM32WL.” “After further investigation, it appears that the Semtech SX1262 does not support LoRa FHSS, (but supports for LR FHSS). This is a hardware limitation rather than a driver limitation.” “There is no reference to LoRa FHSS in the driver code or documentation.” It is also understood that: Semtech SX1262 RF IP (which the STM32WLE5 is based on) does not support LoRa FHSS from a hardware perspective Based on this, my understanding is that: :backhand_index_pointing_right: STM32WLE5JC does not support LoRa FHSS However, I would like clarification on the following: 1. LoRa FHSS Support C

In a recent release (not sure which one) the option to select USER_PHY was added to the platform settings under LWIP.I need to implement a different PHY for a LAN9374. It is basically identical to the LAN8742. The only issue is that the LAN8742 init code fails unless modified slightly. If I select LAN8742 and modify the file I can get it working but as expected every time I regenerate the project the modifications get overwritten. Where is the documentation on how to implement a USER_PHY?

I was wondering if there is any possibility to change the NCS from NCS1_port2 to NCS2_port2 using the OTP registers on the STM32N6.I checked the registers but couldn’t find any option to adjust this. Maybe its not possible. Just to confirm my understanding:The default setting for ROM boot is XSPI1 using XSPIM_Port_2, and NCS1 is "required" by the ROM boot code to correctly load the FSBL via LoadAndRun. https://community.st.com/t5/stm32-mcus-products/stm32n6-it-s-possible-to-change-xspi2-to-xspi1-for-boot-using/m-p/847884/highlight/true#M287378 Kind regards,Zimmeri

Greetings Everybody, Since few months i have been trying my hands on RAK3172. I have successfully implemented ADC, UART/USART and I2C on RAK but without SUBGHZ and everything is working fine. I have also made my custom code for RAK3172 SUBGHZ and it is also working fine. I have established communication with two RAK3172 modules and they are communicating with each other as on successful data transfer between the two i am toggling LED connected to one of the GPIOs. Now problem comes when i am enabling UART/USART and SUBGHZ code. On startup i am sending 64 bytes of data out on UART/USART connected to USB to TTL converter. On every power ON i am trying to find 64 bytes of data on terminal but without any successs. Is there anything that i am doing wrong ?

I am currently using the STM32H735G-DK.​While white and red seem to display correctly, black(0x0000) appears as a dark purple when rendered. Even when displaying textures, there is a slight purple tint mixed in throughout the image.​I am writing to the framebuffer in RGB565 mode, and the LCD is reading directly from it. What could be causing this color distortion?

Dear ST,The STM32H5 overview page seems to display the wrong number(1) of CANFD controllers for STM32H5E4 in the line comparison table. The datasheet says it's 3,  like for all the others  in the STM32H5E/F lines.Also, I couldn't find anything in the errata sheet about non usable CAN instances.

 Hello Forum,I want to use a Nucleo 64 STM32F401 Board to test I2C connection with an unknown master (reverse engineering).The Bus consits of 1 Master (unknown Controller) an 1 Slave (My STM32F40). The Master sends out a Read Request at Addr. 5 and the Slave should respond with 3 Bytes. I've connected the I2C Bus to PB6/PB7 of the Nucleo Board. On Softwareside I Initialized with bare metal Code, see attachment.I my setup a I2C Master sends out a Adress byte with read request to address 5, but my Controller doesn't do a thing at all. I would expect at least an ACK Bit, but nothing can be monitored.From the Signal capture the bus looks fine for me, but in which mode do I need to configure the stm32 slave? Is this standard mode or fast mode. Is the clock speed of any concern in this case (slave)? How to config the CCR and TRISE register in this case.The Port seems to be configured correct, the IDR of GPIOB detects a "1" on PB6/PB7.In my example I've also enabled interrupts, but

After a long time, i started to look into using the BLE_Thread_dynamic stack image on WB55 again. First without success with my own code on my own board, which I do think to remember worked before.But afterwards with the BLE_Thread_dyn example on a WB55 Nucleo Board and that doesn't work as well. This is how the FUS Info looksAnd this is where it gets stuck Any Ideas what I might be doing wrong?I already tested with and without "Start Wireless Stack" from the programmer. Not using it, makes it stop even earlier, at hci_reset.Starting to look into older stack images now.Edit: I went back up to 1.18 (using the example code from 1.24, which seems to be untouched since way back) and nothing worked :thinking_face:.

STM32G491Code generator generate wrong order of calls for SPI initialization for LL driver: LL_DMAMUX_SetSyncRequestNb  calls after LL_DMAMUX_EnableSync