STM32 MCUs Products

Hello,first let me start this post by mentioning that I'm still very much a beginner.I'm writing my own abstraction layer functions for the N657X0.While running my clock_config() function, I ran into an issue that I don't know how to fix. The function works as follows:- reset RCC->CR, CRGR1, CFGR2- enable MSI and wait for MSI ready bit- set CPU & SYS clock source to MSI and wait for clock source confirmation bits- disable all other oscillators and all PLL- reset RCC->HSICFGR- configure HSI- enable HSI and wait for HSI ready bit- set CPU & SYS clock source to HSI and wait for clock source confirmation bits- disable MSI- reset RCC->MSICFGR- configure MSI- enable/disable oscillators (if HSIEN=0 then MSIEN=1 and vice-versa)- reset RCC->ICxCFGR- configure ICx- reset RCC->PLLxCFGRx- configure PLLx- enable PLLx and wait for PLLx lock ready bit- check CPU and SYS clock source selection- check if source is actually active by checking the corresponding ready bit again- sel

Hello,I dug deeper into PSSI behavior, and and I observed unwanted behavior. From my point of view it is a bug.PSSI is configured as:OUTEN = 1 (transmit mode)CKPOL = 0 (outputs driven on rising edge, inputs sampled on falling edge)RDYPOL = 0 (0 at input indicates that the receiver is ready to receive)DEPOL = 0 (0 at output indicates that data is valid)DERDYCFG = 0b11 (Both PSSI_RDY and PSSI_DE alternate functions enabled)EDM = 0b00 (Interface captures 8-bit data on every parallel data clock)Chip STM32H7R3Z8T6, clocked at 600MHz from HSI, placed at PCB, powered by 3.3VPSSI kernel clocked by 150MHz and 300MHz (PLL from HSI)Transmitted data is rising numbers from 0 to 15, stored in array in AHBSRAM1, manualy written by core to PSSI->DR as 32bit values (four data bytes at one write). See source code:while (1){ if(PSSI->SR & PSSI_SR_RTT4B){ // wait until space in PSSI buffer PSSI->DR = arr[idxx]; // place data to buffer idxx++; // index to next data if(idxx >= BLOCK_SIZE

Hello,I designed a custom PCB using the STM32F401RE (LQFP64), but I cannot connect to the MCU through SWD. I am using an ST-Link probe and the st-probe command-line tool.When I run the probe command, the ST-Link probe itself is detected, but the target MCU is not properly identified. The tool reports the flash size as 0x00.MCU: STM32F401REDebugger: ST-Link probeTool: st-probeObserved behavior:ST-Link probe is detected correctly.The MCU is not detected.Flash size reported as 0x00.Power measurements:VDD = 3.3 VVDDA = 3.3 V (through ferrite bead BLM18AG601SN1D)VCAP ≈ 1.2 V (2.2 µF capacitor connected directly, ~8 mm trace, no vias)NRST = 3.3 VTotal board current ≈ 18 mA (two LEDs also present)The MCU does not heat up, and current consumption appears normal.Power architecture:12 V input → buck converter → 5 V → LDO → 3.3 V (MCU supply)Analog supply filtering:VDD → ferrite bead → VDDADecoupling capacitors are placed near the MCU.Debug connections:SWDIO → PA13SWCLK → PA14NRST connected to th

We are developing a STiROT/OEMuROT bootloader for a customer using the above chip. This is based on the STM32H7S78-DK sample. The customer has developed the main application and have added support to download a new firmware image over Ethernet. This image is stored in external RAM and once downloaded an md5 checksum of the image is stored and a flag is set to indicate that new firmware is available. At this point the device is restarted to switch to the bootloader. We've added code to the bootloader that checks if a new firmware image is available in external RAM. If a new image is available the bootloader validates that the image is OK by recalculating the md5 checksum. The validation passes and at this point a section in external FLASH is erased. After the erase completes, the image in external RAM is copied into the external FLASH and the copied image is validated via md5 checksum - which fails. On further investigation it is the data being read from external RAM that is incorrect (

I'm trying to set up FSMC in muxed mode to read_write external NOR flash devices. Muxed pins goes through 2 8-bit latches 74HC574D.The problem is that currently i can barely read from external NOR and it's not accepting commands.Firstly HAL_NOR_Init(&hnor1, &Timing, NULL) returns HALL_ERR  since it fails to read CommandSet from NOR. It should read address 0x13 from CFI and get 0x02 or 0x01 as a result, but write commad makes no effect and as a result driver reads at 0x13 from memopry start.After analyzing what's going on on the FSMC bus I still cand fing any clues. Here is an example how it performs ReadID sequence, using standard HAL_NOR_ReadID Everything looks correct, 3 sequences 0x555 - >0xAA, 0x2AA -> 0x55 and 0x555 -> 0x90, but reading 0x00 and 0x01 right after returns data from NOR not the deviceID I've also tried bitbang mode with same pins and code below successfully reads deviceID. So after all it's not a witing problem, but maby timings or so

Hello ST,1. ds14258 Rev.6 Table 57 on p.163 specifies a positive I_inj of "N/A" for pins other than PA4, PA5, PB2, PB12,PC14, PC15, PD8, and PH2 (as opposed to a positive I_inj of "0 mA" in the row above for pins PA4, PA5, PB2, PB12, PC14, PC15, PD8, and PH2) Does "N/A" mean that it is *impossible* to cause any positive injection (on pins other than PA4, PA5, PB2, PB12,PC14, PC15, PD8, and PH2) with pin voltages between 0V and 4V when VDD is unpowered or at 0V?i.e. Do pins other than PA4, PA5, PB2, PB12, PC14, PC15, PD8, and PH2 have some kind of "nice" input structure that allows powering them when VDD is unpowered or at 0V?  2. ds14258 Rev.6 states in Note 3 on p.128: "Positive injection (when VIN > VDDIOx) is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value." Does "not possible" in the above sentence mean:a. that externally raising the voltage on those pins to between 0V and 4V when VDD is unpowe

  I found more issues. 1. Missing SRAMEN bit in RCC_AHBENR register. I think it is bit 9. See STM32U0 RM0503 page 54, RCC_AHBSMENR register and STM32F0 RM0091. With this new bit, reset value is: 0x0000 0300Also I think that it is missing SRAMRST bit in RCC_AHBRSTR register. It should be bit 9. This problem is also on STM32G0 and STM32C0 RMs. 2. Missing TIMx_OR2 and TIMx_OR3 registers mentioned on RM0503 page 553.This problem is also on STM32G0 RM0444 and RM0454, and STM32C0 RM0490. 3. STM32F0 RM0091 didn't mention how internal break input (called "Internal break event sources") is selected. See pages 359 and 514. STM32F0 RM0091 doesn't have an equivalent to STM32U0 RM0503 figure 164 on page 592. 4. STM32U0 RM0503 pages 107, 108 and 118, mentions pin PE6 but it doesn't exist in datasheet. RTC_TAMP3/TAMP_IN3 is pin PB15 and not pin PE6. From STM32U0 DS:TAMP_IN1 PC13TAMP_IN2 PA0TAMP_IN3 PB15TAMP_IN4 PC5TAMP_IN5 PA1 5. STM32U0 RM0503 page 413: Missing description of VREFBUF_CCR regist

Hello,I would like to confirm how VBUS behaves in STM32 USB OTG depending on the Host/Device mode.Specifically, I would like to ask the following:When STM32 is configured as Host mode, should the STM32 source 5 V onto VBUS?When STM32 is configured as Device mode, does it only sense/monitor VBUS as an input?Is this behavior handled automatically by the internal OTG controller, or does it require an external VBUS power switch or additional external circuitry?Additionally, I would like to ask about a hardware configuration where an external 5 V supply is always present on VBUS, regardless of the STM32 Host/Device configuration.In this case, I would like to confirm:Whether this could cause any issues when STM32 operates in Host modeWhether it could affect Host/Device role detection or OTG behaviorWhether USB enumeration and normal data communication would still function correctlyIn other words, I would like to know whether a design where VBUS is always supplied by an external 5 V source is

Hello,I the Reference Manual (RM0410 Rev 5) for STM32F769I-DISCO, DMA_P1 is not shown connected to AHB Bus Matrix. It is intentional or error in the diagram ?Thanks,Debasish Das  

Hey I am having trouble tryng to connect my stm32g473 to a canbus. I am using a l9616 as a transceiver and the bus is functions as I have connected to it with an stm32f722re with the same l9616.The clock is 64Mhz,Ive used the canbit time calculation website to define the values of nominal time 1 and 2 to achive 500kbs.Also using NVIC and it seems to be configured fine. When tested in loopback the interrupt is called and the messages are received.This is the init with the filter config,as I ve understand I am not filtering anything and any of the messages on the bus should get to my uC.When running the state of hfdcan1 is Busy and also no error code show up.FDCAN_HandleTypeDef hfdcan1; /* FDCAN1 init function */ void MX_FDCAN1_Init(void) { /* USER CODE BEGIN FDCAN1_Init 0 */ /* USER CODE END FDCAN1_Init 0 */ /* USER CODE BEGIN FDCAN1_Init 1 */ /* USER CODE END FDCAN1_Init 1 */ hfdcan1.Instance = FDCAN1; hfdcan1.Init.ClockDivider = FDCAN_CLOCK_DIV1; hfdcan1.Init.FrameFormat =

Hello Community,I am migrating a prototype CMake application to TrustZone for a test board targeting the STM32U575VGT6 MCU.  Launching a debug session for my project generates the following errors.  `I've attached verbose console error output in the attached file (console_error_output.txt).CubeProgrammer confirms I have the set Option Byte for TZEN .The debug configuration should be flashing the secure image before the non-secure.GTZC_NS/S are enabled. I have been following the tutorial Develop TrustZone enabled applications on STM32L5 ARM MCUs with STM32CubeIDE - Webinar Replay .  The instructions at 20:00 are completely arcane and I realize I am out of my depth of expertise to get this small project to work (.ioc attached).Does anyone have an application note or tutorial, pertinent to the U5 series, that explains how to flash and launch debugger sessions for a pure CMake + TZ project using only STM32CubeIDE 2.1.0, CubeMX 6.17.0, and CubeProgrammer 2.22.0

In the document UM3234 we see the following description of clock configurationOn my Nucleo board, I haven't blown any fuses and measured a clock frequency of 32 MHz. Since the XSPI is configured to have a prescaler of 2 by BOOTROM (also mentioned in UM3234), this implies that the board is using the default clock scenario. The document also mentions this regarding the nominal scenario."During secure boot, the boot ROM sets up PLL1 to switch to CM55, APB, AHB, and AXI clocking at the nominalboot frequency"Does this mean that if i dont have secure boot enabled yet, ill get the default clock, and as soon as I enable secure boot my clock frequency will increase to 400 MHz?. 

Hi Folks, I'm working on pattern generation on GPIO pins and I've done it successfully using bare-metal programming approach. I used TIM1 to trigger DMA2 to take data from a buffer and send it GPIOA->BSRR.  But when I try to change the timer from TIM1 to TIM2 and change the respective DMA stream, the same code does not work. code:   uint32_t signal1[6]; //pattern no included // Enable clocks for GPIOA, TIM2, and DMA1 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN; RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; // Configure GPIOA Pins 0-5 as output GPIOA->MODER &= ~0x00000FFF; // Clear mode for PA0-PA5 GPIOA->MODER |= 0x00000555; // Set PA0-PA5 as General Purpose Output // Configure TIM2 for DMA requests on update event TIM2->PSC = 0; // Set prescaler to 0 TIM2->ARR = 999; // Set auto-reload value (adjust for timing) TIM2->DIER |= TIM_DIER_UDE; // Enable update DMA request TIM2->CR1 |= TIM_CR1_CEN; // Enable TIM2 // Configure

Hello,Using a NUCLEO H7S3L8, I'm trying to run a test where, using circular DMA with a linked list, I'm trying to send a buffer in memory over to the SAI for audio playback, using an external DAC. This configuration is based on either other tutorials or the reference manual, but it always throws a User Error flag and calls the DMA's IRQ handler, right after the HAL_DMAEx_List_Start_IT() call (whether done on its own after the necessary configuration, or as part of HAL_SAI_Transmit_DMA()). Even with some changes, it always yields the same results. The only one that seemed to have any effect was setting the Transfer Event mode to trigger the TC flag for each linked list item, which confirmed that a transfer might have been completed, despite the error flag.I have also seen GPDMA being configured with circular, using both Standard Request Mode and a Linked List, but haven't gotten any success out of that myself (with even TC flag not being raised).In case it causes any comp

Hi guy I want to use Nucleo h755zi-q to sent modbus TCP/IP but I have a little time and I'm a beginner. I watched some GitHub but I don't understand. Some one can help me pls 

I am currently performing the bring-up of a custom PCBA using the STM32H755ZIT3.My design is intended to use the Internal LDO only, bypassing the SMPS to reduce component count (i.e. one less inductor in my layout).Here's few details about the MCU power section of my SCH (also, please check attached capture):SMPS Pins: As per the Reference Manual for "LDO-only" mode, I have grounded VFBBSMPS, VSSSMPS and VDDSMPS, whereas VLXSMPS is floating.VCORE/VCAP: I have placed the required 2.2uF decoupling capacitors on VCAP_1, VCAP_2, and VCAP_3. No external inductor is present on the layout.What I'm observing is that at power-on, VCORE remains at 0V. Consequently, the target is not detected by the ST-LINK. If I instead "jumpstart" the board by applying an external 1.2V to the VCAP nodes, the MCU becomes reachable via SWD, and I can successfully modify registers. I suspect a conflict between my hardware layout and the factory default reset value of the PWR_CR3

I am using the STM32G474 in STM32CubeIDE with the built-in CubeMx environment. MX_DAC1_Init() to setup the DAC1_Ch1. Internal VREF+ is 2.9V. When it is buffered DAC, I get output very close to 2.9V at max(4095). However if i switch to unbuffered mode, the output is only 1.4+V(about half of 2.9V) at max setting of 4095. There was no mention in the reference manual RM0440 about the change in gain for buffered or unbuffered DAC. Is this normal?

I'm trying to read a NTC temperature sensor, but the readings I'm getting are very inconsistent and at times just way off.  I have nucleo on the way but this testing I'm doing is on a blue pill.The sensor is sitting in a cup of water, so temperature should be very consistent.  Here is the readings I'm getting which are done at 1 second intervals, I don't need speed.  The temperature of the water is about 21C.  The sensor accuracy is rated +/- 1.4C at 25CTemp k: 293. c: 20.8Temp k: 293. c: 20.7Temp k: 294. c: 21.2Temp k: 292. c: 19.5Temp k: 307. c: 34.1Temp k: 295. c: 22.3Temp k: 294. c: 20.8Temp k: 293. c: 20.7Temp k: 294. c: 21.5Temp k: 293. c: 20.7Temp k: 294. c: 21.3Temp k: 294. c: 21.4Temp k: 293. c: 20.8Temp k: 293. c: 20.5Temp k: 294. c: 21.1Temp k: 292. c: 19.7Temp k: 266. c: -6.5Temp k: 293. c: 20.5Temp k: 293. c: 20.8Temp k: 291. c: 18.8Temp k: 266. c: -7.1Temp k: 293. c: 20.6Temp k: 294. c: 21.3Temp k: 294. c: 21.3Temp k: 293. c: 20.6Temp k: 294. c: 20.9At

Dear Sirs, we have a SPI CRC problem we thried heavily to solve, but no success.We broke it down to just send one byte of data, so the CRC is known in advance and it is easy to debug.Here the description what we did:DevicesMaster: STM32F7 (SPI1)Slave: STM32F4Communication mode: SPI full duplexData width: 8 bitCRC enabled on both sidesCRC ConfigurationCRC polynomial: 0x07Data size: 8 bitMSB firstOnly one data byte used for testingTest frameData byte transmitted by slave:0x55Expected CRC (CRC-8, polynomial 0x07):0xACSPI clockThe SPI clock on the master is set to the lowest possible speed:Prescaler = 256Therefore there should be no timing issue with the CRCNEXT bit being set during the last data frame is clocked.We use HAL 1.3.3 and HAL_SPI_TransmitReceive_IT on the master sideObserved SPI signals (oscilloscope)On the SPI bus we observe exactly the expected sequence:0x550xACSo the slave transmits the correct CRC value.Master behaviourWhen the first SPI interrupt occurs on the master

Trying to run timer2 to set pwm signal for the BLUE LED (PA5).The MCU is STM32U083MCT6 and I used rm for STM32U083MC series (https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf)I set each bit and register separately to be sure that everything is set correctly, but still miss something related to TIM2.What settings to check related to TIM2 and what is the best approach to configure timers of this MCU?

Hi, I am using STM32CubeMX 6.16.1 with a STM32H503RB and I have exactly the same problem :  RCC is configured with LL library (not HAL), here is the SystemClock_Config() function generated by STM32CubeMX :  void SystemClock_Config (void) { LL_FLASH_SetLatency(LL_FLASH_LATENCY_5); while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_5) { } LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0); while (LL_PWR_IsActiveFlag_VOS() == 0) { } LL_RCC_HSE_Enable(); /* Wait till HSE is ready */ while (LL_RCC_HSE_IsReady() != 1) { } LL_RCC_LSI_Enable(); /* Wait till LSI is ready */ while (LL_RCC_LSI_IsReady() != 1) { } LL_RCC_PLL1_SetSource(LL_RCC_PLL1SOURCE_HSE); LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4); LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE); LL_RCC_PLL1_SetM(12); LL_RCC_PLL1_SetN(250); LL_RCC_PLL1_SetP(2); LL_RCC_PLL1_SetQ(4); LL_RCC_PLL1_SetR(2); LL_RCC_PLL1P_Enable(); LL_RCC_PLL1_Enable(); /* Wait till PLL is read

According to Datasheet, I2C of STM32F413VGT can be increased to 1 MHz, is it possible?    

 This is the pinout for the STM32F469I-DISCO and OV2640, I have been able to find pins for most of them but am having trouble:DCMI Pinout: (Pin function : Actual pin name)DCMI_D0 : PC6DCMI_D1: PC7DCMI_D2: PG10DCMI_D3: PG11DCMI_D4: MissingDCMI_D5: PD3DCMI_D6: Conflict with PB8DCMI_D7: Conflict with PB9DCMI_VSYNC: PG9DCMI_HSYNC: PA4DCMI_PIXCLK: PA6RCC_MCO_1: PA8 (Note: we can use this pin to generate the XCLK signal needed by the OV2640SIOC: PB8SIOD: PB9I would appreciate it if anyone has a solution for this, thanks

Hi,I'm working on a piece of code using UART, where I need to send a byte of information right after the negative edge of that line is detected. Basically, my dev kit is connected to a 1-wire device through a simple 2 N-FET transistor for the TX side and directly to RX. Additionally, I have another GPIO connected to the 1-wire interface to detect, via interrupt, when the 1-wire device pulls the line down (start bit). The 1-wire device releases the bus right after the start bit.The problem that I'm facing is that the timing at which the byte is sent by the MCU is very inconsistent, with a delay that is not tolerable by the application. I've tried several things with no improvements:        - Send UART command using non-blocking mechanisms (interrupt and DMA)        - Making the GPIO interrupt the one with the highest priority        - Disable interrupts before sending UART command and enabling afterwards i.e.: __disable_irq() a

Hello, I have some setup variables in my app which should retained while the power is switched off. Normally I would use the dedicated Backup RAM, but the board does not have backup battery, battery socket, not a battery connector. The Backup RAM is not usable with STM32n6570-DK board. The MCU does not have internal flash memory with backup area. (This worked with H747 and H723 MCUs) The board has an external 1Mbit flash memory controlled by OCTOSPI so I might store data in the external flash. I need max 512 bytes only. This 512-byte backup should be placed to the end of the external flash. Can anybody advice how to do this? Best regards, Louis